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參數(shù)資料
| 型號： | MAX9250GCM/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER LVDS 48LQFP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 250 |
| 功能： | 解串器 |
| 數(shù)據速率： | 840Mbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVCMOS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 27 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
______________________________________________________________________________________
15
Input Frequency Detection
A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
except LOCK are low, LOCK is high, and PCLK_OUT
follows REFCLK. This condition occurs, for example, if
the serializer is not driving the interconnect or if the
interconnect is open.
Frequency Range Setting (RNG[1:0])
The RNG[1:0] inputs select the operating frequency
range of the MAX9248/MAX9250 and the transition time
of the outputs. Select the frequency range that includes
the MAX9247 serializer PCLK_IN frequency. Table 3
shows the selectable frequency ranges and the corre-
sponding data rates and output transition times.
Power Down
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN
≤ 0.3V and all
LVTTL/LVCMOS inputs
≤ 0.3V or ≥ VCC - 0.3V, the sup-
ply current is reduced to less than 50A. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
Lock and Loss-of-Lock (LOCK)
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low,
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Lock to REFCLK takes a
maximum of 16,928 REFCLK cycles for the MAX9250.
The MAX9248 has an additional spread-spectrum PLL
(SSPLL) that also begins locking to REFCLK. Locking
both PLLs to REFCLK takes a maximum of 33,600 REFCLK
cycles for the MAX9248.
When the MAX9248/MAX9250 complete their lock to
REFCLK, the serial input is monitored for a transition
word. When a transition word is found, LOCK output is
driven low, indicating valid output data and the parallel
rate clock recovered from the serial input is output on
PCLK_OUT. The MAX9248 SSPLL waits an additional
288 clock cycles after the transition word is found
before LOCK is driven low and sequence takes effect.
PCLK_OUT is stretched on the change from REFCLK to
recovered clock (or vice versa) at the time when the
transition word is found.
If a transition word is not detected within 222 cycles of
PCLK_OUT, LOCK is driven high, the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the MAX9250 and Figure 8 for the MAX9248 regarding
the synchronization timing diagram.
The MAX9248 input-to-output delay can be as low as
(4.5tT + 8.0)ns or as high as (36tT + 16)ns due to
spread-spectrum variations (see Figure 6).
The MAX9250 input-to-output delay can be as low as
(3.575tT + 8)ns or as high as (3.725tT + 16)ns.
PARALLEL CLOCK FREQUENCY (MHz)
CAPACITOR
VALUE
(nF)
21
24
27
33
36
39
30
120
80
60
40
20
100
140
0
18
42
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
RNG1
RNG0
PARALLEL
CLOCK
(MHz)
SERIAL-
DATA RATE
(Mbps)
OUTPUT
TRANSITION
TIME
0
2.5 to 5.0
50 to 100
0
1
5 to 10
100 to 200
Slow
1
0
10 to 20
200 to 400
1
20 to 42
400 to 840
Fast
Figure 16. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
Table 3. Frequency Range Programming
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9251 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9252 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9253 | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9254 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| MAX9254EUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
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