參數(shù)資料
型號(hào): MAX9250ECM/V+T
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 0K
描述: IC DESERIALIZER LVDS 27B 48LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,000
功能: 解串器
數(shù)據(jù)速率: 840Mbps
輸入類(lèi)型: LVDS
輸出類(lèi)型: LVCMOS
輸入數(shù): 1
輸出數(shù): 27
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
_______________________________________________________________________________________
7
Pin Description
PIN
MAX9248
MAX9250
NAME
FUNCTION
11
R/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT
for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a
falling latch edge. Internally pulled down to GND.
2
RNG1
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internally pulled down to GND.
33
VCCLVDS
LVDS Supply Voltage. Bypass to LVDSGND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
4
IN+
Noninverting LVDS Serial-Data Input
5
IN-
Inverting LVDS Serial-Data Input
6
LVDSGND
LVDS Supply Ground
7
PLLGND
PLL Supply Ground
88
VCCPLL
PLL Supply Voltage. Bypass to PLLGND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
9
RNG0
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel
clock input frequency. Internal pulldown to GND.
10
GND
Digital Supply Ground
11
VCC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to
GND with 0.1F and 0.001F capacitors in parallel as close to the device as possible with
the smallest value capacitor closest to the supply pin.
12
REFCLK
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within
±2% of the
serializer PCLK_IN frequency. Internally pulled down to GND.
13
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
14
SS
LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of PCLK_OUT and
output data relative to PCLK_IN. Drive SS high for 4% spread and pull low for 2% spread.
15–23
CNTL_OUT0–
CNTL_OUT8
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the
rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held
at the last state when DE_OUT is high.
24
DE_OUT
LVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active. Low
indicates CNTL_OUT[8:0] are active.
25, 37
VCCOGND
Output Supply Ground
26, 38
VCCO
Output Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as
close to the device as possible with the smallest value capacitor closest to the supply pin.
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MAX9250ETM 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
MAX9250ETM-T 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵(lì)器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel
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MAX9250GCM/V+T 功能描述:串行器/解串器 - Serdes 27Bit 2.5-42MHz DC Bl LVDS Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
MAX9250GCM+ 功能描述:串行器/解串器 - Serdes 27Bit 2.5-42MHz DC Bl LVDS Deserializer RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64