參數(shù)資料
型號： MAX9248GCM/V+T
廠商： Maxim Integrated Products
文件頁數(shù)： 15/20頁
文件大?。?/td> 0K
描述： IC DESERIALIZR LVDS 27BIT 48TQFP
標準包裝： 2,000
系列： *
MAX9248/MAX9250
27-Bit, 2.5MHz to 42MHz
DC-Balanced LVDS Deserializers
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage
VID = 0.1V to 1.2V, input common-mode voltage
VCM =
VID / 2 to VCC - VID / 2, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, VID = 0.2V,
VCM = 1.2V, TA = +25°C.) (Notes 3, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFCLK TIMING REQUIREMENTS
MAX9248/MAX9250ECM
23.8
400.0
Period
tT
MAX9248/MAX9250GCM
28.6
400.0
ns
MAX9248/MAX9250ECM
2.5
42.0
Frequency
fCLK
MAX9248/MAX9250GCM
2.5
35.0
MHz
Frequency Variation
ΔfCLK
REFCLK to serializer PCLK_IN
-2.0
+2.0
%
Duty Cycle
DC
40
50
60
%
Transition Time
tTRAN
20% to 80%
6
ns
SWITCHING CHARACTERISTICS
MAX9248/
MAX9250ECM
2.2
4.6
RNG1 = high
MAX9248/
MAX9250GCM
2.2
4.9
MAX9248/
MAX9250ECM
2.8
5.2
Output Rise Time
tR
Figure 3
RNG1 = low
MAX9248/
MAX9250GCM
2.8
6.1
ns
RNG1 = high
MAX9248/
MAX9250ECM
1.9
4.0
MAX9248/
MAX9250ECM
2.3
4.3
Output Fall Time
tR
Figure 3
RNG1 = low
MAX9248/
MAX9250GCM
2.3
5.2
ns
PCLK_OUT High Time
tHIGH
Figure 4
0.4 x
tT
0.45 x
tT
0.6 x
tT
ns
PCLK_OUT Low Time
tLOW
Figure 4
0.4 x
tT
0.45 x
tT
0.6 x
tT
ns
Data Valid Before PCLK_OUT
tDVB
Figure 5
0.35 x tT
0.4 x tT
ns
Data Valid After PCLK_OUT
tDVA
Figure 5
0.35 x tT
0.4 x tT
ns
MAX9248, Figure 8
33,600 x tT
PLL Lock to REFCLK
tPLLREF
MAX9250, Figure 7
16,928 x tT
ns
Maximum output
frequency
fREFCLK
+ 3.6%
fREFCLK
+ 4.0%
fREFCLK
+ 4.4%
SS = high,
Figure 11
Minimum output
frequency
fREFCLK
- 4.4%
fREFCLK
- 4.0%
fREFCLK
- 3.6%
Maximum output
frequency
fREFCLK
+ 1.8%
fREFCLK
+ 2.0%
fREFCLK
+ 2.2%
Spread-Spectrum Output
Frequency (MAX9248)
fPCLK_OUT
SS = low,
Figure 11
Minimum output
frequency
fREFCLK
- 2.2%
fREFCLK
- 2.0%
fREFCLK
- 1.8%
MHz
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