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參數(shù)資料
| 型號： | MAX9246GUM/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER 21BIT 48TSSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________
17
RT is required to match the transmission line impedance
(usually 100
Ω) and RO is determined by the LVDS dri-
ver design (the minimum differential output resistance of
78
Ω for the MAX9209/MAX9213 serializers is used in
the following example). This condition leaves the capac-
itor selection to change the system time constant.
In the following example, the capacitor value for a 2%
droop is calculated. Jitter due to this droop is then cal-
culated assuming a 1ns transition time:
C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 1)
where:
C = AC-coupling capacitor (F)
tB = bit time (s)
DSV = digital sum variation (integer)
ln = natural log
D = droop (% of signal amplitude)
RT = termination resistor (
Ω)
RO = output resistance (
Ω)
Equation 1 is for two series capacitors (Figure 19). The bit
time (tB) is the period of the parallel clock divided by 9.
The DSV is 10. See equation 3 for four series capacitors
(Figure 20).
The capacitor for 2% maximum droop at 16MHz parallel
rate clock is:
C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO))
C = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100
Ω + 78Ω))
C = 0.038F
Jitter due to droop is proportional to the droop and
transition time:
tJ = tT x D (Eq 2)
where:
tJ = jitter (s)
tT = transition time (s) (0 to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ = 1ns x 0.02
tJ = 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
Figure 18. DC-Coupled Link, Non-DC-Balanced Mode
7:1
1:7 FIFO
7
100
Ω
7:1
1:7 FIFO
7
100
Ω
7:1
1:7 FIFO
7
100
Ω
PLL
PLL1 +
SSPLL
100
Ω
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
TxCLK OUT
RxIN__
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT_
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
RO
RT
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PDF描述 |
|---|---|
| MAX9244GUM/V+T | IC DESERIALIZER 21BIT 48TSSOP |
| MAX9242GUM/V+T | IC DESERIALIZER 21BIT 48TSSOP |
| MAX9242EUM+T | IC DESERIALIZER 21BIT 48TSSOP |
| MAX9242GUM+TD | IC 21BIT DESERIALIZER 48-TSSOP |
| MAX9244GUM+TD | IC 21BIT DESERIALIZER 48-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9247 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer |
| MAX9247_09 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer |
| MAX9247_12 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer |
| MAX9247ECM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer |
| MAX9247ECM/V | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer |
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