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參數(shù)資料
| 型號： | MAX9242EUM/V+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER 21BIT 48TSSOP |
| 標準包裝： | 2,500 |
| 系列： | * |
MAX9242/MAX9244/MAX9246/MAX9254
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
______________________________________________________________________________________
19
Link Power-Up Sequence
The recommended link power-up sequence is to power
up the serializer, wait until the serializer PLL locks, and
then power up the deserializer. This sequence prevents
the deserializer from seeing an undriven or unstable
input when powering up.
PWRDWN
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50A or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
VCC, VCCO, PLLVCC, and LVDSVCC with high-frequency,
surface-mount ceramic 0.1F and 0.001F capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended. Layout PC
board traces for 100
Ω differential characteristic imped-
ance. The trace dimensions depend on the type of
(7 + 2):1
7
100
Ω
(7 + 2):1
7
100
Ω
(7 + 2):1
7
100
Ω
PLL
100
Ω
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246/MAX9254
TxOUT
TxCLK OUT
RxIN__
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT_
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
PLL1 +
SSPLL
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
1:(9 - 2)
+ FIFO
RO
RT
Figure 20. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9242GUM | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| MAX9242GUM/V+ | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9242GUM/V+T | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9242GUM+D | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9242GUM+TD | 功能描述:串行器/解串器 - Serdes 21-Bit DC-Balanced LVDS Deserializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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