- 您現在的位置：買賣IC網 > PDF目錄11687 > MAX9218ETM+T (Maxim Integrated Products)IC DESERIALIZER LVDS 48-TQFN PDF資料下載
參數資料
| 型號： | MAX9218ETM+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 12/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER LVDS 48-TQFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 功能： | 解串器 |
| 數據速率： | 700Mbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVCMOS |
| 輸入數： | 1 |
| 輸出數： | 27 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-TQFN-EP（6x6） |
| 包裝： | 帶卷 (TR) |
MAX9218
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
6
_______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1R/F
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for
latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch
edge. Internally pulled down to GND.
2
RNG1
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internally pulled down to GND.
3VCCLVDS
LVDS Supply Voltage. Bypass to LVDS GND with 0.1F and 0.001F capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
4
IN+
Noninverting LVDS Serial Data Input
5
IN-
Inverting LVDS Serial Data Input
6
LVDS GND
LVDS Supply Ground
7
PLL GND
PLL Supply Ground
8VCCPLL
PLL Supply Voltage. Bypass to PLL GND with 0.1F and 0.001F capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
9
RNG0
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internal pulldown to GND.
10
GND
Digital Supply Ground
11
VCC
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with
0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smallest value
capacitor closest to the supply pin.
12
REFCLK
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within
±2% of the serializer
PCLK_IN frequency. Internally pulled down to GND.
13
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
14
OUTEN
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places
the single-ended outputs in high impedance. Internally pulled down to GND.
15–23
CNTL_OUT [8:0]
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising or
falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state
when DE_OUT is high.
24
DE_OUT
LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates
CNTL_OUT[8:0] are active.
25, 37
VCCO GND
Output Supply Ground
26, 38
VCCO
Output Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close to the
device as possible, with the smallest value capacitor closest to the supply pin.
27
LOCK
LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
28
PCLK_OUT
LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
29–36,
39–48
RGB_OUT [17:0]
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into
the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the
last state when DE_OUT is low.
—
EP
Exposed Pad for Thin QFN Package Only. Connect to GND.
發(fā)布緊急采購，3分鐘左右您將得到回復。