參數(shù)資料
型號: MAX9217ETM+T
廠商: Maxim Integrated Products
文件頁數(shù): 5/15頁
文件大小: 0K
描述: IC SERIALIZER LVDS 48-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
功能: 串行器
數(shù)據(jù)速率: 700Mbps
輸入類型: LVTTL/LVCMOS
輸出類型: LVDS
輸入數(shù): 27
輸出數(shù): 1
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-TQFN-EP(6x6)
包裝: 帶卷 (TR)
MAX9217
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
______________________________________________________________________________________
13
Power-Down and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated 100
Ω output termination, and puts the output
in high impedance to ground and differentially. With
PWRDWN
≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or
≥ VCCIN - 0.3V, supply current is reduced to 50A or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100
Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100
Ω differen-
tial. The 100
Ω integrated termination pulls OUT+ and
OUT- together while the PLL is locking so that VOD = 0V.
If VCC = 0, the output resistor is switched out and the LVDS
outputs are high impedance to ground and differentially.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 16,385 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Input Buffer Supply
The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNG0, RNG1, PCLK_IN, and PWRDWN) are
powered from VCCIN. VCCIN can be connected to a
1.71V to 3.6V supply, allowing logic inputs with a nomi-
nal swing of VCCIN. If no power is applied to VCCIN
when power is applied to VCC, the inputs are disabled
and PWRDWN is internally driven low, putting the
device in the power-down state.
Power-Supply Circuits and Bypassing
The MAX9217 has isolated on-chip power domains. The
digital core supply (VCC) and single-ended input supply
(VCCIN) are isolated but have a common ground (GND).
The PLL has separate power and ground (VCCPLL and
VCCPLL GND) and the LVDS input also has separate
power and ground (VCCLVDS and VCCLVDS GND). The
grounds are isolated by diode connections. Bypass each
VCC, VCCIN, VCCPLL, and VCCLVDS pin with high-frequen-
cy, surface-mount ceramic 0.1F and 0.001F capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100
Ω ±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
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