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參數(shù)資料
| 型號： | MAX9214EUM+D |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER PROG 48TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 39 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 1.785Gbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL，LVCMOS |
| 輸入數(shù)： | 3 |
| 輸出數(shù)： | 21 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
PWRDWN
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50A or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock time specification. When the PLL is locking, the
outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
VCC, VCCO, PLL VCC, and LVDS VCC pin with high-fre-
quency, surface-mount ceramic 0.1F and 0.001F
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer printed-
circuit board (PCB) with separate layers for power,
ground, LVDS inputs, and digital signals is recom-
mended.
ESD Protection
The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler-
ance is rated for IEC 61000-4-2, Human Body Model and
ISO 10605 standards. IEC 61000-4-2 and ISO 10605
specify ESD tolerance for electronic systems. The IEC
61000-4-2 discharge components are CS = 150pF and
RD = 330
Ω (Figure 14). For IEC 61000-4-2, the LVDS
inputs are rated for ±8kV Contact Discharge and ±15kV
Air Discharge. The Human Body Model discharge com-
ponents are CS = 100pF and RD = 1.5k
Ω (Figure 15). For
the Human Body Model, all pins are rated for ±5kV
Contact Discharge. The ISO 10605 discharge compo-
nents are CS = 330pF and RD = 2k
Ω (Figure 16). For ISO
10605, the LVDS inputs are rated for ±8kV Contact
Discharge and ±25kV Air Discharge.
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND. DCB/NC is not 5V tolerant. The input voltage
range for DCB/NC is nominally ground to VCC.
Normally, DCB/NC is connected to VCC or ground.
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50
Ω TO 100Ω
RD
2k
Ω
CS
330pF
Figure 16. ISO 10605 Contact Discharge ESD Test Circuit
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________
13
CS
150pF
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50
Ω TO 100Ω
RD
330
Ω
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1M
Ω
RD
1.5k
Ω
CS
100pF
Figure 15. Human Body ESD Test Circuit
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