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參數(shù)資料
| 型號(hào)： | MAX9213EUM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 0K |
| 描述： | IC SERIALIZER PROG 48-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 功能： | 串行器 |
| 數(shù)據(jù)速率： | 1.785Gbps |
| 輸入類型： | LVTTL/LVCMOS |
| 輸出類型： | LVDS |
| 輸入數(shù)： | 21 |
| 輸出數(shù)： | 3 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
______________________________________________________________________________________
15
RO = output resistance (
)
Equation 1 is for two series capacitors (Figure 14). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 15).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = -(2 x tB x DSV) / (ln (1 - D) x (RT + RO))
C = -(2 x 13.9ns x 10) / (ln (1 - .02) x (100
+ 78))
C = 0.0773F
Jitter due to droop is proportional to the droop and
transition time:
tJ = tT x D (Eq 2)
where:
tJ = jitter (s)
tT = transition time (s) (0% to 100%)
D = droop (% of signal amplitude)
Jitter due to 2% droop and assumed 1ns transition time is:
tJ = 1ns x 0.02
tJ = 20ps
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 15) is:
C = -(4 x tB x DSV) / (ln (1 - D) x (RT + RO)) (Eq 3)
Integrated Termination
The MAX9209/MAX9213 have an integrated output ter-
mination resistor across each of the four LVDS outputs.
These resistors damp reflections from induced noise and
mismatches between the transmission line impedance
and termination resistor at the deserializer input. In DC-
balanced mode, the differential output resistance is part
of the RC time constant. In non-DC-balanced mode, the
output termination is increased to 410
(typ) to reduce
power. In power-down mode (PWRDWN = low) or when
the power supply is off, the output resistor is switched
out and the LVDS outputs are high impedance.
PWRDWN and Power-Off
Driving PWRDWN low stops the PLL, switches out the
integrated output termination resistors, puts the LVDS
outputs in high impedance, and reduces supply current
to 50A or less. Driving PWRDWN high starts the PLL
lock to the input clock and switches in the output termi-
nation resistors. The LVDS outputs are not driven until
the PLL locks. The differential output resistance pulls
the outputs together and the LVDS outputs are high
impedance to ground. If the power supply is turned off,
the output resistors are switched out and the LVDS out-
puts are high impedance.
PLL Lock Time
The PLL lock time is set by an internal counter. The maxi-
mum time to lock is 32,800 clock periods. Power and
clock should be stable to meet the lock-time specifica-
tion. When the PLL is locking, the LVDS outputs are not
active and have a differential output resistance of RO.
Power-Supply Bypassing
There are separate power domains for LVDS, PLL, and
digital circuits. Bypass each LVDS VCC, PLL VCC, and
VCC pin with high-frequency surface-mount ceramic
0.1F and 0.001F capacitors in parallel as close to the
device as possible, with the smallest value capacitor
closest to the supply pin.
LVDS Outputs
The LVDS outputs are current sources. The voltage
swing is proportional to the load impedance. The out-
puts are rated for a differential load of 100
±1%.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100
. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS input and LVDS output sig-
nals separated to prevent crosstalk. A four-layer PCB
with separate layers for power, ground, LVDS outputs,
and digital signals is recommended.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9214 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Programmable DC-Balance 21-Bit Deserializers |
| MAX9214ETM | 制造商:Maxim Integrated Products 功能描述:PROGRAMMABLE DC-BALANCE 21-BIT DESERIALIZER - Rail/Tube |
| MAX9214EUM | 制造商:Maxim Integrated Products 功能描述:PROGRAMMABLE DC-BALANCE 21-BIT DESERIALIZER - Rail/Tube |
| MAX9214EUM+ | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9214EUM+D | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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