參數(shù)資料
型號(hào): MAX9213EUM+T
廠商: Maxim Integrated Products
文件頁數(shù): 4/18頁
文件大小: 0K
描述: IC SERIALIZER PROG 48-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
功能: 串行器
數(shù)據(jù)速率: 1.785Gbps
輸入類型: LVTTL/LVCMOS
輸出類型: LVDS
輸入數(shù): 21
輸出數(shù): 3
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
MAX9209/MAX9213
Programmable DC-Balanced
21-Bit Serializers
12
______________________________________________________________________________________
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode volt-
age range by AC-coupling. AC-coupling increases the
common-mode voltage range of an LVDS receiver to
nearly the voltage rating of the capacitor. The typical
LVDS driver output is 350mV centered on an offset volt-
age of 1.25V, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0V to 2.4V, allowing approximately
±1V common-
mode difference between the driver and receiver on a
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Figure 13 shows the DC-coupled link,
non-DC-balanced mode.
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
CYCLE N + 1
CYCLE N
CYCLE N - 1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN0
TxIN1
TxIN2
TxIN6
TxIN3
TxIN4
TxIN5
TxIN7
TxIN8
TxIN9
TxIN13
TxIN10
TxIN11
TxIN12
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
TxIN0
TxIN1
TxIN7
TxIN8
TxIN14
TxIN15
TxIN16
TxIN20
TxIN17
TxIN18
TxIN19
TxCLK OUT+
TxIN0
TxCLK OUT-
TxOUT1
TxOUT0
TxOUT2
Figure 12. Non-DC-Balanced Mode Inputs Mapped to LVDS Outputs
1:7
7
RT =
100
RT =
100
RT =
100
RT =
100
7:1
1:7
7
7:1
1:7
7
PLL
MAX9209
MAX9213
MAX9210
MAX9214
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
RO
Figure 13. DC-Coupled Link, Non-DC-Balanced Mode
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