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參數(shù)資料
| 型號： | MAX9206EAI/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DESERIALIZER LVDS 28-SSOP |
| 其它有關(guān)文件： | Automotive Product Guide |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 46 |
| 功能： | 解串器 |
| 數(shù)據(jù)速率： | 660Mbps |
| 輸入類型： | LVDS |
| 輸出類型： | LVTTL，LVCMOS |
| 輸入數(shù)： | 1 |
| 輸出數(shù)： | 10 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
MAX9206/MAX9208
10-Bit Bus LVDS Deserializers
_______________________________________________________________________________________
9
into high impedance but
LOCK continues to reflect the
status of the serial input. Driving REN high again
enables the ROUT_ and RCLK drivers.
Losing Lock on Serial Data
If one embedded clock edge (rising edge formed by
end/start bits) is not detected,
LOCK goes high, RCLK
tracks REFCLK, and ROUT_ stays active but with
invalid data.
LOCK stays high for a minimum of two
RCLK cycles. Then, if transitions are detected at the
serial input, the PLL attempts to lock to the serial input.
When the PLL locks to serial input data,
LOCK goes
low, RCLK tracks the serializer reference clock (TCLK),
and ROUT_ is valid on the second selected strobe
edge of RCLK after
LOCK goes low. A minimum of two
embedded clock edges in a row are required to regain
lock to the serial input after
LOCK goes high.
For automatic resynchronization,
LOCK can be con-
nected to the MAX9205/MAX9207 serializer SYNC1 or
SYNC2 input. With this connection, when
LOCK goes
high, the serializer sends sync patterns until the deseri-
alizer locks to the serial input and drives
LOCK low.
Input Fail-Safe
When the serial input is undriven (a disconnected cable
or serializer output in high impedance, for example) an
on-chip fail-safe circuit (Figure 2) drives the serial input
high. The response time of the fail-safe circuit depends
on interconnect characteristics. With an undriven input,
LOCK may switch high and low until the fail-safe circuit
takes effect. The undriven condition of the link can be
detected in spite of
LOCK switching since LOCK is
high long enough to be sampled (
LOCK is high for at
least two RCLK cycles after a missed clock edge and
RCLK keeps running, allowing sampling). If it is
required that
LOCK remain high for an undriven input,
the on-chip fail-safe circuit can be supplemented with
external pullup bias resistors.
Deserializer Jitter Tolerance
The tJT parameter specifies the total zero-to-peak input
jitter the deserializer can tolerate before a sampling
error occurs (Figure 9). Zero-to-peak jitter is measured
from the mean value of the deterministic jitter distribu-
tion. Sources of jitter include the serializer (supply
noise, reference clock jitter, pulse skew, and intersym-
bol interference), the interconnect (intersymbol interfer-
ence, crosstalk, within-pair skew, ground shift), and the
deserializer (supply noise). The sum of the zero-to-peak
individual jitter sources must be less than or equal to
the minimum value of tJT.
For example, at 40MHz, the MAX9205 serializer has
140ps (p-p) maximum deterministic output jitter. The
zero-to-peak value is 140ps/2 = 70ps. If the intercon-
nect jitter is 100ps (p-p) with a symmetrical distribution,
the zero-to-peak jitter is 50ps. The MAX9206 deserializ-
er jitter tolerance is 720ps at 40MHz. The total zero-to-
peak input jitter is 70ps + 50ps = 120ps, which is less
than the jitter tolerance. In this case, the margin is
720ps - 120ps = 600ps.
REFCLK
FREQUENCY
16MHz
35MHz
40MHz
DATA
PATTERN
PSEUDORANDOM
DATA
PSEUDORANDOM
DATA
PSEUDORANDOM
DATA
SYNC
PATTERNS
Maximum
0.749μs
0.375μs
0.354μs
0.134μs
Maximum (Clock
Cycles)
11.99
13.14
14.18
5.37
Average
0.318μs
0.158μs
0.144μs
0.103μs
Average (Clock
Cycles)
5.09
5.52
5.76
4.11
Minimum
0.13μs
0.068μs
0.061μs
Minimum (Clock
Cycles)
2.08
2.37
2.44
2.45
Table 1. Typical Lock Times
Note: Pseudorandom lock performed with 215-1 PRBS pattern, 10,000 lock time tests.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9206EAV | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:10-Bit Bus LVDS Deserializers |
| MAX9207 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:10-Bit.Bus LVDS Serializers |
| MAX9207EAI | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| MAX9207EAI+ | 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9207EAI+T | 功能描述:串行器/解串器 - Serdes 10-Bit Bus LVDS Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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