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M
Quad LVDS Receiver with Hysteresis
8
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Detailed Description
The LVDS is a signaling method intended for point-to-
point communication over a controlled-impedance
medium as defined by the ANSI TIA/EIA-644 and IEEE
1596.3 standards.
The MAX9179 is a quad LVDS line receiver with built-in
hysteresis, intended for high-speed, point-to-point, low-
power applications. The receiver accepts four LVDS
input signals and translates them to 3.3V LVCMOS out-
put levels at speeds up to 400Mbps over controlled-
impedance media of 100
. The hysteresis improves
noise immunity and prevents multiple switching due to
noise on slow input transitions at the end of a long cable.
The receiver is capable of detecting differential signals
as low as 75mV and as high as 1.2V within a 0 to 2.4V
input voltage range. The 250mV to 450mV differential
output of an LVDS driver is nominally centered on a 1.2V
offset. This offset, coupled with the receiver
’
s 0 to 2.4V
input voltage range, allows an approximate ±1V shift in
the signal (as seen by the receiver). This allows for a dif-
ference in ground references of the transmitter and the
receiver, the common-mode effects of coupled noise, or
both. The LVDS standards specify an input voltage
range of 0 to 2.4V referenced to receiver ground.
Hysteresis
The MAX9179 incorporates hysteresis of 50mV (typ),
which rejects noise and prevents false switching during
low-slew-rate transitions at the end of a long cable. The
receiver typically switches at 25mV above or below V
ID
= 0V (Figure 1). The hysteresis is designed to be sym-
metrical around V
ID
= 0V for low pulse distortion (see
the
Typical Operating Characteristics
).
Input Fail-Safe
The fail-safe feature of the MAX9179 sets the output
high when the differential input is:
Open
Undriven and shorted
Undriven and terminated
Without a fail-safe circuit, when the input is undriven,
noise at the input may switch the output and it may
appear to the system that data is being sent. Open or
undriven terminated input conditions can occur when a
cable is disconnected or cut, or when a driver output is
in high impedance. A shorted input can occur because
of a cable failure.
When the input is driven with a differential signal of |V
ID
|
= 75mV to 1.2V within a voltage range of 0 to 2.4V, the
fail-safe circuit is not activated. If the input is open,
undriven and shorted, or undriven and terminated, an
internal resistor in the fail-safe circuit pulls both inputs
above V
CC
- 0.3V, activating the fail-safe circuit and
forcing the output high (Figure 2).
Overshoot and Undershoot
Voltage Protection
The MAX9179 is designed to protect the enable inputs
(EN and
EN
) against latchup due to transient overshoot
and undershoot voltage. If the enable input voltage
goes above V
CC
or below GND by up to 1V, an internal
circuit clamps and limits input current to 1.8mA.
Applications Information
Power-Supply Bypassing
Bypass the V
CC
pin with high-frequency surface-mount
ceramic 0.1μF and 0.001μF capacitors in parallel as
close to the device as possible, with the smaller valued
capacitor closest to V
CC
.
Differential Traces
Input trace characteristics affect the performance of the
MAX9179. Use controlled-impedance differential traces
(100
is typical). To reduce radiated noise and ensure
that noise couples as common mode, route the differ-
ential input signals within a pair close together. Reduce
skew by matching the electrical length of the signal
paths making up the differential pair. Excessive skew
can result in a degradation of magnetic field cancella-
tion. Maintain a constant distance between the differen-
tial traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
ENABLES
EN
INPUTS
(IN_+) - (IN_-)
≥
+75mV
≤
-75mV
OUTPUT
OUT_
H
L
EN
H
L or open
Open, undriven short,
or undriven terminated
H
All other combinations
of enable inputs
X
Z
H
= High logic level
L
= Low logic level
X
= Don't care
Z
= High impedance
Table 1. Functional Table