參數(shù)資料
型號(hào): MAX9173EUE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 通用總線功能
英文描述: Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe
中文描述: QUAD LINE RECEIVER, PDSO16
封裝: 4.40 MM, MO-153AB, TSSOP-16
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 285K
代理商: MAX9173EUE
M
Termination
The MAX9173 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values may range between 90
to 132
,
depending on the characteristic impedance of the
transmission medium.
When using the MAX9173, minimize the distance be-
tween the input termination resistors and the MAX9173
receiver inputs. Use 1% surface-mount resistors.
Board Layout
In general, separate the LVDS inputs from single-ended
outputs to reduce crosstalk. Take special care when
routing traces with the QFN package. Ideally, the LVDS
inputs should be separated by 180
°
from the
LVTTL/LVCMOS outputs to reduce crosstalk.
For LVDS applications, a four-layer PC board that pro-
vides separate layers of power, ground, LVDS inputs, and
output signals is recommended. When using the QFN
package, solder the exposed pad (EP) to the ground
plane using an array of vias for proper heat dissipation.
Chip Information
TRANSISTOR COUNT: 1462
PROCESS: CMOS
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
8
_______________________________________________________________________________________
IN_+
IN_-
OUT_
*50
REQUIRED FOR PULSE GENERATOR.
PULSE
GENERATOR
50
*
50
*
C
L
Figure 2. Propagation Delay and Transition Time Test Circuit
Figure 3. Propagation Delay and Transition Time Test Waveforms
IN_-
1.3V
1.1V
1.2V (0V DIFFERENTIAL)
IN_+
OUT_
1.5V
V
ID
= 0.2V
V
OL
V
OH
20%
20%
80%
80%
t
PHLD
t
PLHD
t
THL
t
TLH
1.5V
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