參數(shù)資料
型號： MAX9163ESA+T
廠商： Maxim Integrated Products
文件頁數(shù)： 5/11頁
文件大小： 0K
描述： IC TXRX LVDS BUS 3.3V 8-SOIC
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 2,500
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 1/1
規(guī)程： LVDS
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 8-SOIC
包裝： 帶卷 (TR)
MAX9163
Bus LVDS 3.3V Single Transceiver
_______________________________________________________________________________________
3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, RE = 0,
|VID| = 0.1V to 2.9V, common-mode input voltage (VCM) = |VID/2| to 3.0V - |VID|/2, RL = 27 ±1%,
TA = -40°C to +85°C. Typical values are at VCC = 3.3V,
|VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY CURRENT
Supply Current
ICC
DE = VCC, RE = 0
13.3
20
mA
Driver Supply Current
ICCD
DE = RE = VCC
13.3
20
mA
Receiver Supply Current
ICCR
DE = RE = 0
4.4
8
mA
Disable Supply Current
ICCZ
DE = 0, RE = VCC
4.4
7.5
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, |VID| = 0.2V, VCM = 1.2V, RL = 27
±1%, CL = 10pF, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, |VID| =
0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted.) (Notes 3, 4, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER, DE = RE = VCC
Differential High-to-Low Propagation Delay
tPHLD
Figure 2
1.0
3.2
5.0
ns
Differential Low-to-High Propagation Delay
tPLHD
Figure 2
1.0
3.0
5.0
ns
Differential Skew | tPHLD - tPLHD |tSKD
Figure 2
0.2
1.0
ns
Rise Time
tTLHD
Figure 2
0.8
2.0
ns
Fall Time
tTHLD
Figure 2
0.6
2.0
ns
Disable Time High to Z
tPHZ
Figure 3
0.5
2.2
9.0
ns
Disable Time Low to Z
tPLZ
Figure 3
0.5
2.2
10.0
ns
Enable Time Z to High
tPZH
Figure 3
2.0
3.2
7.0
ns
Enable Time Z to Low
tPZL
Figure 3
1.0
3.2
9.0
ns
RECEIVER, DE = RE = 0
Differential High-to-Low Propagation Delay
tPHL
Figure 4
2.5
6.4
12.0
ns
Differential Low-to-High Propagation Delay
tPLH
Figure 4
2.5
6.0
10.0
ns
Differential Skew | tPHL - tPLH |tSKD
Figure 4
0.4
2.0
ns
Rise Time
tTLH
Figure 4
1.0
4.0
ns
Fall Time
tTHL
Figure 4
0.4
4.0
ns
Disable Time High to Z
tPHZ
Figure 5
2.0
5.0
6.0
ns
Disable Time Low to Z
tPLZ
Figure 5
2.0
4.4
7.0
ns
Enable Time Z to High
tPZH
Figure 5
2.0
4.6
13.0
ns
Enable Time Z to Low
tPZL
Figure 5
2.0
4.3
10.0
ns
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested
at TA = +25°C.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to device
ground except VTH, VTL, VID, VOD, and
VOD.
Note 3: CL includes probe and jig capacitance.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5: Generator waveforms for all tests unless otherwise specified: f = 100MHz, Z0 = 50
, tR = tF = 6.0ns (0 to 3V, 0% to 100%)
for DE and RE, tR = tF = 3.0ns (0 to 3V, 0% to 100%) for DIN, and tR = tF = 1.0ns (|VID| = 0.2V, 20% to 80%) for DO+/RI+
and DO-/RI- inputs.
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