參數(shù)資料
型號： MAX9126EUE+
廠商： Maxim Integrated Products
文件頁數(shù)： 6/12頁
文件大?。?/td> 0K
描述： IC QUAD LVDS LINE RCVR 16-TSSOP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 96
類型： 接收器
驅動器/接收器數(shù)： 0/4
規(guī)程： LVDS
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 管件
MAX9125/MAX9126
Quad LVDS Line Receivers with
Integrated Termination
_______________________________________________________________________________________
3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA =
-40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, CL = 10pF, differential input voltage |VID| = 0.2V to 1.0V, common-mode voltage VCM = |VID/2| to 2.4V
-
|VID/2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, TA = -40°C to +85°C. Typical values are at VCC =
+3.3V, VCM = 1.2V, |VID| = 0.2V, TA = +25°C, unless otherwise noted.) (Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (EN, EN)
Input High Voltage
VIH
2.0
VCC
V
Input Low Voltage
VIL
0
0.8
V
Input Current
IIN
VIN = VCC or 0
-15
15
A
SUPPLY
Supply Current
ICC
Enabled, inputs open
9
15
mA
Disabled Supply Current
ICCZ
Disabled, inputs open
70
500
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
tPHLD
Figures 2 and 3
1.8
2.4
3.3
ns
Differential Propagation Delay
Low to High
tPLHD
Figures 2 and 3
1.8
2.3
3.3
ns
Differential Pulse Skew
[tPHLD - tPLHD] (Note 5)
tSKD1
Figures 2 and 3
100
300
ps
Differential Channel-to-Channel
Skew (Note 6)
tSKD2
Figures 2 and 3
400
ps
Differential Part-to-Part Skew
(Note 7)
tSKD3
Figures 2 and 3
0.8
ns
Differential Part-to-Part Skew
(Note 8)
tSKD4
Figures 2 and 3
1.5
ns
Rise Time
tTLH
Figures 2 and 3
0.34
1.2
ns
Fall Time
tTHL
Figures 2 and 3
0.32
1.2
ns
Disable Time High to Z
tPHZ
RL = 2k
, Figures 4 and 5
12
ns
Disable Time Low to Z
tPLZ
RL = 2k
, Figures 4 and 5
12
ns
Enable Time Z to High
tPZH
RL = 2k
, Figures 4 and 5
17
ns
Enable Time Z to Low
tPZL
RL = 2k
, Figures 4 and 5
17
ns
Maximum Operating Frequency
(Note 9)
fMAX
All channels switching
250
300
MHz
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