參數(shù)資料
型號(hào): MAX9101EUK+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 8/8頁(yè)
文件大?。?/td> 0K
描述: IC COMPARATOR OD SOT23-5
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 通用
元件數(shù): 1
輸出類型: CMOS,開(kāi)漏極,軌至軌,TTL
電壓 - 電源,單路/雙路(±): 1 V ~ 5.5 V
電壓 - 輸入偏移(最小值): 10mV @ 5.5V
電流 - 輸入偏壓(最小值): 0.015µA @ 5.5V
電流 - 靜態(tài)(最大值): 13µA
CMRR, PSRR(標(biāo)準(zhǔn)): 68dB CMRR,66dB PSRR
傳輸延遲(最大): 4.5µs
磁滯: ±2mV
工作溫度: -40°C ~ 85°C
封裝/外殼: SC-74A,SOT-753
安裝類型: 表面貼裝
包裝: 帶卷 (TR)
MAX9100/MAX9101
+1.0V Micropower SOT23 Comparators
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
leads are long. Minimize signal lead lengths to reduce
stray capacitance between the input and output that
might cause instability.
Typical Application
Logic-Level Translator
3V to 5V
Figure 3 shows an application that converts 3V logic
levels to 5V logic levels. The push-pull output MAX9100
is powered by the +5V supply voltage, and the invert-
ing input is biased to +1.5V with two resistors. This con-
figuration allows a full 5V swing at the output,
maximizing the noise margin of the receiving circuit.
1V to 3V
Figure 4 shows an application that converts 1V logic
levels to 3V logic levels. The MAX9101 is powered by
the +1V supply voltage, and the pullup resistor for the
output is connected to the +3V supply voltage. The
inverting input is biased to +0.5V with two resistors.
Chip Information
TRANSISTOR COUNT: 393
PROCESS: BiCMOS
MAX9100
IN-
232k
100k
5V
LOGIC OUT
OUT
VCC
+5V
GND
3V LOGIC IN
IN+
MAX9101
IN-
100k
100k
3V
LOGIC OUT
OUT
VCC
+1.0V
GND
1V LOGIC IN
IN+
RPULLUP
+3V
Figure 3. MAX9100 Logic-Level Translator
Figure 4. MAX9101 Logic-Level Translator
N.C.
IN-
N.C.
VCC
N.C.
OUT
IN+
GND
SO-8
2
3
4
1
8
7
6
5
MAX9100
MAX9101
Pin Configurations (continued)
Revision History
Pages changed at Rev 1: 1–8
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