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參數(shù)資料
| 型號： | MAX901BESE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR VOLT 16-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 通用 |
| 元件數(shù)： | 4 |
| 輸出類型： | TTL |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 10 V，±2.5 V ~ 5 V |
| 電壓 - 輸入偏移（最小值）： | 4mV @ ±5V |
| 電流 - 輸入偏壓（最小值）： | 10µA @ ±5V |
| 電流 - 靜態(tài)（最大值）： | 15mA，12mA，6mA |
| CMRR, PSRR（標準）： | 82.5dB CMRR，80dB PSRR |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
MAX900–MAX903
High-Speed, Low-Power Voltage Comparators
_______________________________________________________________________________________
9
Definitions of Terms
VOS
Input Offset Voltage: Voltage applied
between the two input terminals to obtain
TTL-logic threshold (+1.4V) at the
output.
tpd+ (D)
Latch Disable-to-Output High Delay:
The propagation delay measured from
the latch-signal crossing the TTL
threshold in a low-to-high transition to
the point of the output crossing TTL
threshold in a low-to-high transition.
VIN
Input Voltage Pulse Amplitude: Usually
set to 100mV for comparator
specifications.
tpd- (D)
Latch Disable-to-Output Low Delay:
The propagation delay measured from
the latch-signal crossing the TTL
threshold in a low-to-high transition to
the point of the output crossing TTL
threshold in a high-to-low transition.
VOD
Input Voltage Overdrive: Usually set to
5mV and in opposite polarity to VIN for
comparator specifications.
ts
Minimum Setup Time: The minimum
time before the negative transition of the
latch signal that an input signal change
must be present in order to be acquired
and held at the outputs.
tpd+
Input-to-Output High Delay: The
propagation delay measured from the
time the input signal crosses the input
offset voltage to the TTL-logic threshold
of an output low-to-high transition
th
Minimum Hold Time: The minimum time
after the negative transition of the latch
signal that an input signal must remain
unchanged in order to be acquired and
held at the output.
tpd-
Input-to-Output Low Delay: The
propagation delay measured from the
time the input signal crosses the input
offset voltage to the TTL-logic threshold
of an output high-to-low transition.
tpw (D)
Minimum Latch-Disable Pulse Width:
The minimum time that the latch signal
must remain high in order to acquire and
hold an input-signal change.
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