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參數(shù)資料
| 型號： | MAX9013EUA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR TTL 8-UMAX |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補充型，TTL |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 3mV @ 5.5V |
| 電流 - 輸入偏壓（最小值）： | 0.5µA @ 5V |
| 電流 - 輸出（標準）： | 40mA |
| 電流 - 靜態(tài)（最大值）： | 2.3mA |
| CMRR, PSRR（標準）： | 95dB CMRR，82dB PSRR |
| 傳輸延遲（最大）： | 9ns |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
MAX9010–MAX9013
SC70, 5ns, Low-Power, Single-Supply,
Precision TTL Comparators
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (MAX9010/MAX9011) (continued)
(VCC = 5V, VLE = 0 (MAX9011 only), VCM = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Latch Setup Time (Note 8)
tSU
MAX9011 only
2
0
ns
Latch Hold Time (Note 8)
tH
MAX9011 only
2
0.5
ns
Latch Propagation Delay
(Note 8)
tLPD
MAX9011 only
5
ns
Input Noise-Voltage Density
en
f = 100kHz
6
nV/
√Hz
VOVERDRIVE = 100mV
5
8
CLOAD = 5pF,
TA = +25°C
VOVERDRIVE = 5mV
5.5
9
VOVERDRIVE = 100mV
9
Propagation Delay (Note 6)
tPD+, tPD-
CLOAD = 5pF,
TA = TMIN to TMAX
VOVERDRIVE = 5mV
10
ns
Output Rise Time
tR
0.5V
≤ VOUT ≤ 2.5V
3
ns
Output Fall Time
tF
2.5V
≥ VOUT ≥ 0.5V
2
ns
MAX9010EXT
0.8
Input Capacitance
CIN
MAX9011EUT
1.2
pF
Power-Up Time
tON
1s
ELECTRICAL CHARACTERISTICS (MAX9012/MAX9013)
(VCC = 5V, VLE = 0 (MAX9013 only), VCM = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage Range
VCC
Inferred from PSRR test
4.5
5.5
V
MAX9012
2.4
4.2
Power-Supply Current (Note 2)
ICC
MAX9013
1.3
2.3
mA
TA = +25°C
±0.7
±3
Input Offset Voltage
(Note 5)
VOS
TA = TMIN to TMAX
±5.5
mV
Input Offset-Voltage Drift
VOS/T±2
V/
°C
Input Bias Current
IB
±0.5
±2
A
Input Offset Current
IOS
±40
±200
nA
Differential Input Resistance
(Note 4)
RIN(DIFF)
VIN(DIFF) = ±10mV
250
k
Common-Mode Input
Resistance (Note 4)
RIN(CM)
-0.2V
≤ VCM ≤ (VCC - 1.9V)
1
M
Common-Mode Input Voltage
Range (Note 4)
VCM
Inferred from CMRR test
-0.2
VCC - 1.9
V
Common-Mode Rejection
Ratio
CMRR
-0.2V
≤ VCM ≤ (VCC - 1.9V)
75
95
dB
Power-Supply Rejection Ratio
PSRR
VCC = 4.5V to 5.5V
63
82
dB
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