Dual PWM Step-Down Converter in a 2mm x
2mm Package for WCDMA PA and RF Power
12 ______________________________________________________________________________________
Detailed Description
The MAX8896 dual step-down converter is optimized
for powering the power amplifier (PA) and RF transceiv-
er in WCDMA handsets. This device integrates a high-
efficiency PWM step-down converter (OUT1) for
medium and low-power transmission, and a 140m&
(typ) bypass FET to power the PA directly from the bat-
tery during high power transmission. A second high-
efficiency PWM step-down converter (OUT2) supplies
power directly to a high PSRR, low-output noise, 200mA
low-dropout linear regulator (LDO) to power the RF
transceiver.
OUT1 Step-Down Converter
A hysteretic PWM control scheme ensures high efficien-
cy, fast switching, fast transient response, low output
ripple, and physically tiny external components. The
control scheme is simple: when the output voltage is
below the regulation threshold, the error comparator
begins a switching cycle by turning on the high-side
switch. This high-side switch remains on until the mini-
mum on-time expires and output voltage is within regu-
lation, or the inductor current is above the current-limit
threshold. Once off, the high-side switch remains off
until the minimum off-time expires and the output volt-
age falls again below the regulation threshold. During
the off period, the low-side synchronous rectifier turns
on and remains on until the high-side switch turns on
again. The internal synchronous rectifier eliminates the
need for an external Schottky diode.
Voltage-Positioning Load Regulation
The MAX8896 step-down converter utilizes a unique
feedback network. By taking DC feedback from the LX
node through R1 of Figure 1, the usual phase lag due
to the output capacitor is removed, making the loop
exceedingly stable and allowing the use of very small
ceramic output capacitors. To improve the load regula-
tion, resistor R3 is included in the feedback. This con-
figuration yields load regulation equal to half the
inductors series resistance multiplied by the load cur-
rent. This voltage-positioning load regulation greatly
reduces overshoot during load transients or when
changing the output voltage from one level to another.
However, when calculating the required REFIN voltage,
the load regulation should be considered. Because
inductor resistance is typically well specified and the
typical PA is a resistive load, the V
REFIN
to V
OUT1
gain
is slightly less than 2.5V/V. The output voltage is
approximately:
Automatic Bypass Mode
During high-power transmission, the bypass mode con-
nects IN1 directly to PAOUT with the internal 140m&
(typ) bypass FET, while the step-down converter is
forced into 100% duty-cycle operation. The low on-
resistance in this mode provides low dropout, long bat-
tery life, and high output current capability. OUT1
enters bypass mode automatically when V
REFIN
>
0.396 x V
CC
(see Figure 2). Current-limit circuitry con-
tinuously limits current through the bypass FET to
1000mA (typ). The bypass FET opens up if the voltage
at PAOUT drops below 1.25V (typ) in current limit.
OUT2 Step-Down Converter
OUT2 is a high-efficiency, 2MHz current-mode step-
down DC-DC converter that outputs 200mA with effi-
ciency up to 94%. The output voltage of the MAX8896
is a fixed 3.1V for powering the LDO. RFEN1 and
RFEN2 are dedicated enable inputs for OUT2. Drive
RFEN1 or RFEN2 high to enable OUT2, or drive RFEN1
and RFEN2 low to disable OUT2. RFEN1 and RFEN2
have hysteresis so that an RC may be used to imple-
ment manual sequencing with respect to other inputs.
OUT2 operates with a constant 2MHz switching fre-
quency regardless of output load. The MAX8896 regu-
lates the output voltage by modulating the switching
duty cycle. An internal n-channel synchronous rectifier
eliminates the need for an external Schottky diode and
improves efficiency. The synchronous rectifier turns on
during the second half of each switching cycle (off-
time). During this time, the voltage across the inductor
is reversed, and the inductor current ramps down. The
synchronous rectifier turns off at the end of the switch-
ing cycle.
V
V
R  I
OUT
REFIN
L  LOAD
1
25
1
2
=  ?nbsp     ?nbsp ?/DIV>
.
0    10 15 20
5
25 30 35    45
40    50
TIME (ms)
0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
0
V
CC
VOLTAGE
PAOUT
REFIN
Figure 2. Automatic Bypass