參數(shù)資料
型號: MAX8563EEE+
廠商: Maxim Integrated
文件頁數(shù): 6/15頁
文件大?。?/td> 266K
描述: IC REG CTRLR TRPL POS ADJ 16QSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
類型: 正,可調(diào)式
輸出數(shù): 3
輸出電壓: 0.5 V ~ 1.8 V,0.5 V ~ 3.3 V
電流 - 電源: 930µA
輸入電壓: 5V,12V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-QSOP
包裝: 管件
?%, Ultra-Low Output Voltage, Dual and Triple
Linear n-FET Controllers
6  _______________________________________________________________________________________
Pin Description (continued)
NAME
PIN
MAX8563
MAX8564/
MAX8564A
FUNCTION

EN2
Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the
output. Connect to V
DD
 for always-on operation.
7
DRV3

O utp
ut 3 n- M O S FE T D r i ve. D r i ves the g ate of an exter nal n- channel M O S
FE T to r eg ul ate outp ut 3.
DRV3 is internally pulled to ground when EN3 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.

FB2
Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and
GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the
Output Voltage Setting section.
8
FB3

Feedback Input for Output 3. Connect to the center of a resistor-divider between output 3 and
GND to set the output voltage of output 3. The feedback regulation voltage is 0.500V. See the
Output Voltage Setting section.

DRV2
O utp
ut 2 n- M O S FE T D r i ve. D r i ves the g ate of the exter nal n-
channel M OS FE T to r
eg ul ate outp
ut 2.
DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.
9
EN3

Enable Control for Output 3. Drive logic high to enable output 3, or logic low to disable the
output. Connect to V
DD
 for always-on operation.

V
DD
+5V or +12V Supply Input. Connect to external +5V or +12V supply rail. Bypass with a 0.1礔
ceramic or larger capacitor.
10
POK3

Output 3 Power-Good Signal. Open-drain output pulls low when output 3 is 12% below the
nominal regulated voltage.
11
N.C.

No Internal Connection
12
POK2

Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the
nominal regulated voltage.
13
EN2

Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the
output. Connect to a V
DD
 for always-on operation.
14
FB2

Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and
GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the
Output Voltage Setting section.
15
DRV2

O utp
ut 2 n- M O S FE T D r i ve. D r i ves the g ate of the exter nal n-
channel M OS FE T to r
eg ul ate outp
ut 2.
DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit
for compensation. See the Stability Compensation section.
16
V
DD

+5V or +12V Supply Input. Connect to an external +5V or +12V supply rail. Bypass with a 0.1礔
ceramic or larger capacitor.
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MAX8563EEE+ 功能描述:低壓差控制器 - LDO Dual & Triple Linear n-FET Controller RoHS:否 制造商:Micrel 最大輸入電壓:5.5 V 輸出電壓:Adjustable 輸出電流:10 mA 負載調(diào)節(jié): 輸出類型:Adjustable, Fixed 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格:SMD/SMT 封裝 / 箱體:SOT-23-6
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