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參數(shù)資料
| 型號(hào)： | MAX8533EUB+T |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 6/10頁 |
| 文件大小： | 240K |
| 描述： | IC HOT-SWAP CNTRLR 12V 10-UMAX |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用型 Infiniband? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 10 V ~ 14 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
Smallest, Most Reliable, 12V, Infiniband-
Compliant Hot-Swap Controller
6 _______________________________________________________________________________________
Pin Description
PIN
NAME
FUNCTION
1
ISET
Current-Limit Threshold Programming Input. Connect to the low side of the current-limit threshold
programming resistor.
2
IN
Bulk Power Supply. Connect to the input power supply and positive terminal of the current-sense resistor.
3
GATE
External MOSFET-Gate-Drive Output. Connect to the gate of the external N-channel MOSFET. A series
resistor and capacitor connected from GATE to RET sets the turn-on ramp rate. At turn-on, this capacitor is
charged to V
IN
+ 5V (typ) by an internal current source. GATE is pulled to RET when EN is high and/or LPEN
is low. GATE is pulled to RET during a fault condition.
4
CTIM
Current Regulation Time Programming Input. Connect a capacitor from CTIM to RET. The capacitance at
CTIM determines the time delay between an overcurrent event and chip output shutdown (current-limit
timeout). CTIM is pulled low, resetting the fault latch when either EN is high or LPEN is low.
5
RET
Bulk Power Ground
6
OVP
Overvoltage Protection Input. Connect to common point of a resistor-divider from OUT to RET. GATE pulls
low when V
OVP
exceeds the 2V threshold for at least 1.5ms and the IC is latched off.
7
OUT
Output Voltage. Connect to the output of the circuit.
8
POK
P ow er - Good Outp ut. P O K i s an op
en- d r
ai n outp ut that b ecom es hi g h i
m p ed
ance w
hen V
OU
T
r eaches 9.6V . P
ul l
P OK up to the sup p l y r ai l usi ng an exter nal p ul l up r esi stor
. P OK i
s p
ul l
ed to RE
T unti l
the M AX 8533 i s enab
l ed
.
9
LPEN
Local Power-Enable Input. LPEN is a positive-assertion enable input to turn on the IC. Pull LPEN low to
disable the output. LPEN has an internal pullup to 5V.
10
EN
Chip-Enable Input. EN is an active-low input that enables the IC.
Detailed Description
The MAX8533 is a single-port, 12V, IB-compliant versa-
tile hot-swap controller IC designed for applications
where a line card is inserted into a live backplane. The
MAX8533 can be implemented in both IB Class I (non-
isolated) and Class II (isolated) power-topology appli-
cations. Normally, when a line card is plugged into a
live backplane, the low impedance of the cards dis-
charged filter capacitors can momentarily collapse the
input supply voltage. The MAX8533 is designed to
reside on the line card and to provide inrush current-
limiting and short-circuit protection. This is achieved
using an external N-channel MOSFET, current-sense
resistor, and current-limit set resistor, along with two
on-chip comparators (Figure 1).
UVLO and Startup
The MAX8533 has an undervoltage lockout protection
circuit. The circuit is disabled when V
IN
is below 8.4V
(typ). The gate of the MOSFET, CTIM, LPEN, and POK is
pulled to RET until V
IN
exceeds the UVLO threshold.
Once V
IN
exceeds the UVLO threshold and LPEN and
EN are enabled, the capacitor on the gate of the exter-
nal MOSFET is charged and the MOSFET turns on. The
charging of this capacitor provides soft-start to prevent
high inrush currents.
On/Off Control
The MAX8533 is enabled/disabled using LPEN and EN.
Drive EN low and LPEN high to enable the device. LPEN
can also be left unconnected as it is internally connected
to 5V. Drive LPEN low or EN high to disable the output.
Table 1 is the truth table for these inputs.
EN
LPEN
OUTPUT
0
0
OFF
0
1
ON
1
0
OFF
1
1
OFF
Table 1. Truth Table
Zero is a logic-low input, 1 is a logic-high input or unconnected
input.
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