參數(shù)資料
型號(hào): MAX814
廠商: Maxim Integrated Products, Inc.
英文描述: Accuracy, Low-Power, +3V and +5V μp Supervisory Circuits(高精度,±1%,低功耗,3V和5VμP監(jiān)控電路)
中文描述: ±1%精度、低功耗、+3V與+5V微處理器監(jiān)控電路
文件頁數(shù): 14/16頁
文件大?。?/td> 154K
代理商: MAX814
M
Negative-Going V
CC
T ransients
In addition to issuing a reset to the μP during power-up,
power-down, and brownout conditions, the MAX814/
MAX815/MAX816 series is relatively immune to short
duration negative-going V
CC
transients (glitches). The
Typical Operating Characteristics show a graph of
Maximum Transient Duration vs. Reset Comparator
Overdrive, for which a reset is not generated. The
graph was made using a negative-going pulse applied
to V
CC
, starting 1.5V above the actual reset threshold
and ending below it by the magnitude indicated (reset
comparator overdrive). The graph indicates the typical
maximum pulse width a negative-going V
CC
transient
may have without causing a reset pulse. As the magni-
tude of the transient increases (goes further below the
reset threshold), the maximum allowable pulse width
decreases. Typically, a V
CC
that goes 100mV below the
reset threshold and lasts 30μs or less will not cause a
reset pulse to be issued.
A 0.1μF bypass capacitor mounted as close as possible
to pin 2 (V
CC
) provides additional transient immunity.
Interfac ing to μPs
with Bidirec tional Reset Pins
μPs with bidirectional reset pins, such as the Motorola
68HC11 series, can cause a conflict with the RESET
output. If, for example, the RESET output is driven high
and the μP wants to pull it low, indeterminate logic lev-
els may result. To correct this, connect a 4.7k
resistor
between the RESET output and the μP reset I/O, as in
Figure 14. Buffer the RESET output to other system
components.
±1% Ac c urac y, Low-Power, +3V and +5V
μP S upervisory Circ uits
14
______________________________________________________________________________________
Figure 12. Monitoring a Negative Voltage
Figure 13. Flow Chart of WDI Implementation
MAX814
MAX815
MAX816
RESET
R2
R1
+5V
V-
V
CC
PFI
GND
MR
PFO
TO
μ
P
100k
100k
2N3904
MR
PFO
+5V
0V
+5V
0V
V
TRIP
0V
V-
V
PFT
= 2.5V (K, L, N); 1.70V (T AND MAX816)
TRIP ,
V
TRIP
< 0V
5 - 2.5 = 2.5 - V
BEGIN PROGRAM
SET LOW
WDI
SET HIGH
WDI
SUBROUTINE
SET LOW
WDI
YES
NO
RETURN
Figure 14. Interfacing to μPs with Bidirectional Reset I/O
MAX814
MAX815
MAX816
BUFFERED RESET TOOTHER SYSTEM COMPONENTS
4.7k
V
CC
GND
RESET
V
CC
GND
RESET
μ
P
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