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This address determines the location of the charac-
ter on the display (see Figures 10 and 21).
5) Write the Character Address byte (CA[7:0]) to be
written to the display memory into DMDI[7:0]. It will
be stored along with a Character Attribute byte
derived from DMM[5:3] (see Figure 19). The dis-
play-memory address is automatically incremented
following the write operation. Repeat until the final
display-memory address is reached.
6) Write DMDI[7:0] = FFH to terminate the auto-incre-
ment mode. Note that the character stored at
CA[7:0] = FFH is not available for use when in auto-
increment mode.
Steps for Reading from Display
Memory in 8-Bit Mode
1) Write DMM[6] = 1 to select the 8-bit operation mode.
2) Write DMAH[1] = 0 to read the Character Address
byte or DMAH[1] = 1 to read the Character Attribute
byte.
3) Write to DMAH[0] to select the MSB of the address
where data must be read from (Figure 10).
4) Write to DMAL[7:0] to select all the lower order bits,
except for the MSB, of the address where data must
be read from (Figure 10).
5) Read DMDO[7:0] to read the data from the selected
location in the display memory (Figure 10).
Steps for Reading from Display
Memory in 16-Bit Mode
1) Write DMM[6] = 0 to select the 16-bit operation
mode.
2) Write DMAH[0] = x to select the MSB and
DMAL[7:0] = xxH to select the lower order bits of
the address where the character data is to be read.
This address determines the location of the charac-
ter on the display (see Figure 10).
3) Read DMDO[15:0] to read the Character Address
byte and the Character Attribute byte from the
selected location in the display memory. The first
data byte is the Character Address (CA[7:0]), and
the second byte contains the Character Attribute
bits (Figure 20). Note that the bit positions of the
Character Attribute byte when read, differ from
when they are written. See the
Display Memory Data
Out Register (DMDO)
section and Figure 20 for a
description of the bit locations of the attribute bits
when reading.
Note:
If an internal display-memory read request
occurs simultaneously with an SPI display-memory
operation, the internal read request is ignored, and the
display of that character, during that field time, may
appear to momentarily break up. See the
Synchronous
OSD Updates
section.
Synchronous OSD Updates
The display of a character may momentarily appear to
break up if an internal display-memory read request
occurs simultaneously with an SPI display-memory
operation. Momentary breakup of the OSD image can
be prevented by writing to the display memory during
the vertical blanking interval. This can be achieved by
using
VSYNC
as an interrupt to the host processor to
initiate writing to the display memory. Alternatively, the
OSD image can be synchronously disabled before writ-
ing to the display memory and synchronously re-
enabled afterwards (see VM0[3:2]).
Multiple OSDs with
Common Clock Application
The MAX7456 provides a TTL clock output (CLKOUT)
capable of driving one CLKIN pin of another MAX7456.
Two or more MAX7456 parts can be driven using an
external clock driver. This arrangement reduces the
system cost by having only one crystal on one
MAX7456 that supplies the clock signal to multiple
MAX7456 parts (Figure 25).
Single-Channel Monochrome On-Screen
Display with Integrated EEPROM
40
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Table 5. Display-Memory Access Modes and SPI Operations
OPERATING
MODE
AUTO-INCREMENT
MODE DISABLED
DMM[0] = 0
No. OF READ
OPERATIONS
No. OF WRITE
OPERATIONS
AUTO-INCREMENT
MODE ENABLED
DMM[0] = 1
No. OF WRITE
OPERATIONS
One-time setup
Per character
One-time setup
Per character
2
3
1
6
1
3
1
6
One-time setup
Per character
One-time setup
Per character
6
1
6
1
16-Bit Mode
DMM[6] = 0
8-Bit Mode
DMM[6] = 1