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參數(shù)資料
| 型號： | MAX7326ATG+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 16B 24TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 16 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 1.71 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-TQFN-EP（4x4） |
| 包裝： | 帶卷 (TR) |
| 包括： | POR |
MAX7326
I2C Port Expander with 12 Push-Pull Outputs
and 4 Inputs
8
_______________________________________________________________________________________
selection logic uses AD0 to select whether pullups are
enabled for ports I2 and I3, and to set the initial logic
level for those ports, and AD2 for ports I4 and I5. The
rule is that a logic-high, SDA, or SCL connection
selects the pullups and sets the default logic state to
high. A logic-low sets the default to low (Tables 2 and
3). This means that the port configuration is correct on
power-up for a standard I2C configuration, where SDA
or SCL are pulled up to V+ by the external I2C pullup
resistors.
The power-up default states of the 12 push-pull outputs
are set according to the I2C slave address selection
inputs, AD0 and AD2 (Tables 2 and 3).
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. Also, if SDA and SCL are terminated
with pullup resistors to a different supply voltage than
the MAX7326’s supply voltage, and if that pullup supply
rises later than the MAX7326’s supply, then SDA or SCL
may appear at power-up to be connected to GND. In
applications like this, use the four address combinations
that are selected by strapping address inputs AD0 and
AD2 to V+ or ground (shown in
bold in Tables 2 and 3).
These selections are guaranteed to be correct at power-
up, independent of SDA and SCL behavior. If one of the
other 12 address combinations is used, an unexpected
combination of pullups might be asserted until the first
I2C transmission (to any device, not necessarily the
MAX7326) is put on the bus, and an unexpected combi-
nation of ports may initialize as logic-low outputs instead
of inputs or logic-high outputs.
Port Inputs
Port inputs switch at CMOS-logic levels as determined
by the expander’s supply voltage, and are overvoltage
tolerant to +6V, independent of the expander’s supply
voltage.
Port-Input Transition Detection
All four input ports are monitored for changes since the
expander was last accessed through the serial inter-
face. The state of the input ports is stored in an internal
“snapshot” register for transition monitoring. The snap-
shot is continuously compared with the actual input
conditions, and if a change is detected for any port
input, then an internal transition flag is set for that port.
The four port inputs are sampled (internally latched into
the snapshot register) and the old transition flags are
cleared during the I2C acknowledge of every MAX7326
read and write access. The previous port transition
flags are read through the serial interface as the sec-
ond byte of a 2-byte read sequence.
PIN
CONNECTION
DEVICE ADDRESS
PORT POWER-UP DEFAULT
40k
INPUT PULLUPS ENABLED
AD2
AD0
A6
A5
A4
A3
A2
A1
A0
O7
O6
I5
I4
I3
I2
O1
O0
O7 O6
I5
I4
I3
I2
O1
O0
SCL
GND
1
100
000
1
0
Y
—
SCL
V+
1
100
001
1
Y
SCL
1
100
010
1
Y
SCL
SDA
1
100
011
1
Y
SDA
GND
1
100
1
0
Y
—
SDA
V+
1
100
101
1
Y
SDA
SCL
1
100
110
1
Y
SDA
1
100
111
1
Y
GND
1
101
000
0
—
GND
V+
1
101
001
0
1
—
Y
GND
SCL
1
101
010
0
1
—
Y
GND
SDA
1
101
011
0
1
—
Y
V+
GND
1
101
100
1
00
YY
—
V+
1
101
1
11
Y
YYY
V+
SCL
1
101
110
1
Y
V+
SDA
1
101
111
1
Inputs
11
Pullups
are
not
enabled
for
push-pull
outputs.
Y
YYY
Pullups
are
not
enabled
for
push-pull
outputs.
Table 2. MAX7326 Address Map for Ports O0, O1, I2–I5, O6, and O7
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| MAX7326EVCMAXQU+ | 功能描述:界面開發(fā)工具 MAX7326 Max7526 Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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