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參數(shù)資料
型號(hào): MAX7321ATE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/15頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接口: I²C
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 1.71 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(3x3)
包裝: 帶卷 (TR)
包括: POR
MAX7321
I2C Port Expander with 8 Open-Drain I/Os
8
Maxim Integrated
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. Also, if SDA and SCL are terminated
with pullup resistors to a different supply voltage than
the MAX7321’s supply voltage, and if that pullup supply
rises later than the MAX7321’s supply, then SDA or
SCL may appear at power-up to be connected to GND.
In such applications, use the four address combina-
tions that are selected by connecting address inputs
AD2 and AD0 to V+ or GND (shown in bold in Table 3).
These selections are guaranteed to be correct at
power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, an
unexpected combination of pullups might be asserted
until the first I2C transmission (to any device, not neces-
sarily the MAX7321) is put on the bus, and an unex-
pected combination of ports may initialize as logic-low
outputs instead of inputs or logic-high outputs.
Port Inputs
I/O port inputs switch at the CMOS-logic levels as
determined by the expander’s supply voltage, and are
overvoltage tolerant to +6V, independent of the
expander’s supply voltage.
I/O Port Input Transition Detection
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed
through the serial interface. The state of the input ports
is stored in an internal “snapshot” register for transition
monitoring. The snapshot is continuously compared
with the actual input conditions, and if a change is
detected for any port, INT is asserted to signal a state
change. An internal transition flag is set for that port.
The input is sampled (internally latched into the snap-
shot register) and the old transition flags cleared during
the I2C acknowledge of every MAX7321 read and write
access. The previous port transition flags are read
through the serial interface as the second byte of a
2-byte read sequence.
PIN CONNECTION
DEVICE ADDRESS
40k
INPUT PULLUP ENABLES
AD2
AD0
A6
A5
A4
A3
A2
A1
A0
I7
I6
I5
I4
I3
I2
I1
I0
SCL
GND
1
100
000
Y
SCL
V+
1
100
001
Y
SCL
1
0
1
0
Y
SCL
SDA
1
0
1
Y
SDA
GND
1
100
Y
SDA
V+
1
100
101
Y
SDA
SCL
1
0
1
0
Y
SDA
1
0
1
Y
GND
1
101
000
GND
V+
1
101
001
Y
GND
SCL
1
101
010
Y
GND
SDA
1
101
011
Y
V+
GND
1
101
100
Y
V+
1
101
Y
V+
SCL
1
101
110
Y
V+
SDA
1
101
111
Y
Table 3. MAX7321 Address Map
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