參數(shù)資料
型號: MAX7318ATG+
廠商: Maxim Integrated Products
文件頁數(shù): 13/19頁
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 24TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 75
接口: I²C,SM 總線
輸入/輸出數(shù): 16
中斷輸出:
頻率 - 時鐘: 400kHz
電源電壓: 2 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TQFN-EP(4x4)
包裝: 管件
包括: POR
MAX7318
2-Wire-Interfaced, 16-Bit, I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________
3
Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL
signal) to bridge the undefined region SCL’s falling edge.
Note 3: CB = total capacitance of one bus line in pF.
Note 4: The maximum tF for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage tF is
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the SDA/SCL
bus lines without exceeding the maximum specified tF.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Leakage Current
-1
+1
A
Input Capacitance
4pF
INT
Low-Level Output Current
IOL
VOL = 0.4V
6
mA
AC ELECTRICAL CHARACTERISTICS
(V+ = 2V to 5.5V, TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
Figure 2
1.3
s
Hold Time (Repeated) START
Condition
tHD,STA
Figure 2
0.6
s
Repeated START Condition
Setup Time
tSU,STA
Figure 2
0.6
s
STOP Condition Setup Time
tSU,STO
Figure 2
0.6
s
Data Hold Time
tHD,DAT
Figure 2 (Note 2)
0.9
s
Data Setup Time
tSU,DAT
Figure 2
100
ns
SCL Low Period
tLOW
Figure 2
1.3
s
SCL High Period
tHIGH
Figure 2
0.7
s
V+ < 3.3V
500
SDA Fall Time
tF
Figure 2 (Notes 3, 4)
V+
≥ 3.3V
250
ns
Pulse Width of Spike Suppressed
tSP
(Note 5)
50
ns
PORT TIMING
Output Data Valid
tPV
Figure 7
3
s
Input Data Setup Time
27
s
Input Data Hold Time
0s
INTERRUPT TIMING
Interrupt Valid
tIV
Figure 9
30.5
s
Interrupt Reset
tIR
Figure 9
2
s
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