參數(shù)資料
型號(hào): MAX7315ATE+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/26頁(yè)
文件大?。?/td> 0K
描述: IC I/O EXPANDER I2C 8B 16TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
接口: I²C,SM 總線
輸入/輸出數(shù): 8
中斷輸出:
頻率 - 時(shí)鐘: 400kHz
電源電壓: 2 V ~ 3.6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(3x3)
包裝: 帶卷 (TR)
output port registers, and using the software or hard-
ware controls to flip between the patterns.
If the blink phase 1 register is written with 0xFF, then
the BLINK input can be used as a hardware disable to,
for example, instantly turn off an LED pattern pro-
grammed into the blink phase 0 register. This technique
can be further extended by driving the BLINK input with
a PWM signal to modulate the LED current to provide
fading effects.
The blink mode is enabled by setting the blink enable
flag E in the configuration register (Table 4). When blink
mode is enabled, the state of the blink flip flag sets the
phase, and the output ports are set by either the blink
phase 0 register or the blink phase 1 register (Table 7).
The blink mode is disabled by clearing the blink enable
flag E in the configuration register (Table 4). When blink
mode is disabled, the blink phase 0 register alone con-
trols the output ports.
Blink Phase Registers
When the blink function is disabled, the blink phase 0
register sets the logic levels of the 8 ports (P0 through
P7) when configured as outputs (Table 8). A duplicate
register called the blink phase 1 register is also used if
the blink function is enabled (Table 9). A logic high sets
the appropriate output port high impedance, while a
logic low makes the port go low.
MAX7315
8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
______________________________________________________________________________________
15
Table 4. Configuration register (continued)
REGISTER DATA
REGISTER
ADDRESS
CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
CONFIGURATION
R/
W
INTERRUPT
STATUS
INTERRUPT
OUTPUT
CONTROL
AS
GPO
INTERRUPT
ENABLE
GLOBAL
INTENSITY
BLINK
FLIP
BLINK
ENABLE
X
Disable data change interrupt—INT/O8
output is controlled by the O0 and O1 bits
INT
O
O1
O0
I
G
B
E
Enable data change interrupt—INT/O8
output is controlled by port input data
change
XXXX
1
XXX
INT/O8 output is low (blink is disabled)
XXX
00
XX
0
INT/O8 output is high impedance (blink is
disabled)
XXX
10
XX
0
INT/O8 output is low during blink phase 0
XXX
00
XX
1
INT/O8 output is high impedance during
blink phase 0
XXX
10
XX
1
INT/O8 output is low during blink phase 1
XX
0
X
0
XX
1
INT/O8 output is high impedance during
blink phase 1
XX
1
X
0
XX
1
Read-back data change interrupt status
—data change is not detected, and
INT/O8 output is high when interrupt
enable (I bit) is set
1
0
0
XXXXXX
Read-back data change interrupt status
—data change is detected, and INT/O8
output is low when interrupt enable (I bit)
is set
1
0x0F
1
0
XXXXXX
X = Don’t care.
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