參數(shù)資料
型號(hào): MAX7312AAG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 微控制器/微處理器
英文描述: 2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection
中文描述: 16 I/O, PIA-GENERAL PURPOSE, PDSO24
封裝: 5.30 MM, MO-150, SSOP-24
文件頁數(shù): 3/17頁
文件大?。?/td> 373K
代理商: MAX7312AAG
M
2-Wire-Interfaced 16-Bit I/O Port Expander
with Interrupt and Hot-Insertion Protection
_______________________________________________________________________________________
3
Note 1:
All parameters are 100% production tested at T
A
= +25
°
C. Specifications over temperature are guaranteed by design.
Note 2:
Minimum SCL clock frequency is limited by the MAX7312 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.
Note 3:
A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IL
of the SCL
signal) in order to bridge the undefined region SCL
s falling edge.
Note 4:
C
B
= total capacitance of one bus line in pF.
Note 5:
The maximum t
F
for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t
F
is
specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the
SDA/SCL bus lines without exceeding the maximum specified t
F
.
Note 6:
Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
DC ELECTRICAL CHARACTERISTICS (continued)
(V+= 2V to 5.5V, T
A
= -40
°
C to +125
°
C, unless otherwise noted. Typical values are at V+= 3.3V, T
A
= +25
°
C.) (Note 1)
PARAMETER
SYM B O L
CONDITIONS
MIN
-1
TYP
MAX
+1
UNITS
μA
pF
Leakage Current
Input Capacitance
INT
Low-Level Output Current
4
I
OL
V
OL
= 0.4V
6
mA
AC ELECTRICAL CHARACTERISTICS
(V+= 2V to 5.5V, T
A
= -40
°
C to +125
°
C, unless otherwise noted.) (Note 1)
PARAMETER
SYM B O L
f
SCL
t
TIMEOUT
CONDITIONS
MIN
TYP
MAX
400
61
UNITS
kHz
ms
SCL Clock Frequency
Bus Timeout
(Note 2)
29
Bus Free Time Between STOP
and START Conditions
t
BUF
Figure 2
1.3
μs
Hold Time (Repeated) START
Condition
t
HD,STA
Figure 2
0.6
μs
Repeated START Condition
Setup Time
t
SU,STA
Figure 2
0.6
μs
STOP Condition Setup Time
Data Hold Time
Data Setup Time
SCL Low Period
SCL High Period
t
SU,STO
t
HD,DAT
t
SU,DAT
t
LOW
t
HIGH
Figure 2
Figure 2 (Note 3)
Figure 2
Figure 2
Figure 2
0.6
μs
μs
ns
μs
μs
0.9
100
1.3
0.7
V+ < 3.3V
V+
3.3V
500
250
SDA Fall Time
t
F
Figure 2 (Notes 4, 5)
ns
Pulse Width of Spike Suppressed
PORT TIMING
Output Data Valid
Input Data Setup Time
Input Data Hold Time
INTERRUPT TIMING
Interrupt Valid
Interrupt Reset
t
SP
(Note 6)
50
ns
t
PV
Figure 7
3
μs
μs
μs
27
0
t
IV
t
IR
Figure 9
Figure 9
30.5
2
μs
μs
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