參數(shù)資料
型號(hào): MAX6893
廠商: Maxim Integrated Products, Inc.
英文描述: Pin-Selectable, Octal/Hex/Quad, Power-Supply Sequencers/Supervisors
中文描述: 引腳可設(shè)置八/六/四路電源排序器/監(jiān)控器
文件頁(yè)數(shù): 14/19頁(yè)
文件大?。?/td> 298K
代理商: MAX6893
WDI
t
RP
*t
WDI
*t
WDI
t
WD
t
D-PO
t
RP
t
RP
*t
WDI
*t
WDI
t
WD
t
D-PO
WDO NOT CONNECTED TO MR
WDO CONNECTED TO MR.
V
CC
OR IN2–IN5
2.5V
WDI
V
CC
OR IN2–IN5
2.5V
*t
WDI
IS THE INITIAL WATCHDOG TIMEOUT PERIOD.
RESET
WDO
WDO
RESET
Figure 2. Watchdog, Reset, and Power-Up Timing Diagram
M
Pin-Selectable, Octal/Hex/Quad, Power-Supply
Sequencers/Supervisors
14
______________________________________________________________________________________
Watchdog Timer
The MAX6892/MAX6893/MAX6894s’ watchdog circuit
monitors the microprocessor’s (μP’s) activity. If the μP
does not toggle the watchdog input (WDI) within the
watchdog timeout period, the watchdog output (
WDO
)
asserts. The internal watchdog timer is cleared by
RESET
, or by a transition at WDI (which can detect
pulses as short as 50ns). The watchdog timer remains
cleared while reset is asserted. The timer starts count-
ing as soon as
WDO
is released (see Figure 2).
The MAX6892/MAX6893/MAX6894 feature two modes
of watchdog timer operation: normal mode and initial
mode. At power-up, after a reset event, or after the
watchdog timer expires, the initial watchdog timeout is
active. After the first transition on WDI, the normal
watchdog timeout is active. The initial and normal
watchdog timeouts are determined by the value of the
capacitor connected between SWT and ground or by
connecting SWT to V
CC
(see the
Selecting the Reset and
Watchdog Timeout Capacitor
section). The initial watch-
dog timeout is approximately 64 times the normal watch-
dog timeout. For example, in initial mode a 1μF capacitor
gives a watchdog timeout period of about 5min.
If
WDO
is connected to
MR,
the
WDO
asserts for a
short duration (~5μs), long enough to assert the
RESET
output. Asserting
RESET
clears the watchdog timer and
WDO
goes high. The reset output remains asserted for
its timeout period after a watchdog fault. The watchdog
timer stays cleared as long as
RESET
is low.
The watchdog timeout period is determined by the
value of the capacitor connected between SWT and
ground (see the
Selecting the Reset/Watchdog Timeout
Capacitor
section). Connect SWT to DBP to select fac-
tory-programmed watchdog timeout. To disable the
watchdog timer connect SWT to GND.
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