參數(shù)資料
型號(hào): MAX6817
廠商: Maxim Integrated Products, Inc.
英文描述: 【15kV ESD-Protected, Single/Dual/Octal, CMOS Switch Debouncers
中文描述: ±15kV ESD保護(hù)、單/雙/八通道、CMOS開關(guān)去抖器
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 188K
代理商: MAX6817
Robust S witc h Inputs
The switch inputs on the MAX6816/MAX6817/MAX6818
have overvoltage clamping diodes to protect against
damaging fault conditions. Switch input voltages
can safely swing ±25V to ground (Figure 3). Proprietary
ESD-protection structures protect against high
ESD encountered in harsh industrial environments,
membrane keypads, and portable applications.
They are designed to withstand ±15kV per the
IEC1000-4-2 Air Gap Discharge Test and ±8kV per the
IEC1000-4-2 Contact Discharge Test.
Since there are 63k
(typical) pull-up resistors con-
nected to each input, driving an input to -25V will draw
approximately 0.5mA (up to 4mA for eight inputs) from
the V
CC
supply. Driving an input to +25V will cause
approximately 0.32mA of current (up to 2.6mA for eight
inputs) to flow back into the V
CC
supply. If the total sys-
tem V
CC
supply current is less than the current flowing
back into the V
CC
supply, V
CC
will rise above normal
levels. In some low-current systems, a zener diode on
V
CC
may be required.
±15kV ES D Protec tion
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. The MAX6816/MAX6817/MAX6818 have
extra protection against static electricity. Maxim's engi-
neers have developed state-of-the-art structures to pro-
tect against ESD of ±15kV at the switch inputs without
M
±15kV ES D-Protec ted, S ingle/Dual/Oc tal,
CMOS S witc h Debounc ers
_______________________________________________________________________________________
5
t
DP
IN1
OUT1
IN2
OUT2
CH
MAX6818 ONLY
20ms/div
20V
0
-20V
4V
OUT
(2V/div)
IN
(20V/div)
0
t
EN
OUT NORMALLY
LOW
OUT NORMALLY
HIGH
OUT1–OUT8
1/2
V
CC
1/2
V
CC
1/2
V
CC
1/2
V
CC
1/2
V
CC
EN
t
PE
t
PD
t
PD
V
OL
+ 0.5V
V
OH
- 0.5V
t
PE
t
PC
OUT1–OUT8
CH
Figure 2. Input Characteristics
Figure 3. Switch Input ±25V Fault Tolerance
Figure 4. MAX6818 μP-Interface Timing Diagram
IN1
SW1
SW8
IN8
+V
CC
+V
CC
μ
P
0.1
μ
F
OUT1
OUT8
EN
I/O
IRQ
D0
D7
CH
MAX6818
Figure 5. MAX6818 Typical μP Interfacing Circuit
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