參數(shù)資料
型號(hào): MAX6746KA29+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: ROHS COMPLIANT, SOT-23, 8 PIN
文件頁數(shù): 10/14頁
文件大?。?/td> 170K
代理商: MAX6746KA29+T
MAX6746–MAX6753
P Reset Circuits with Capacitor-Adjustable
Reset/Watchdog Timeout Delay
_______________________________________________________________________________________
5
VCC TO RESET DELAY
vs. TEMPERATURE (VCC FALLING)
MAX6746
toc09
TEMPERATURE (
°C)
V
CC
TO
RESET
DELAY
s)
100
75
50
25
0
-25
25.4
25.8
26.2
26.6
27.0
25.0
-50
125
VCC FALLING AT 1mV/
μs
RESET AND WATCHDOG
TIMEOUT PERIOD vs. SUPPLY VOLTAGE
MAX6746
toc10
VCC (V)
TIMEOUT
PERIOD
(ms)
5.5
5.0
4.0 4.5
2.5 3.0 3.5
2.0
0.44
0.48
0.52
0.56
0.60
0.40
1.5
6.0
CSWT = CSRT = 100pF
Typical Operating Characteristics (continued)
(VCC = +5V, TA = +25°C, unless otherwise noted.)
RESET AND WATCHING TIMEOUT
PERIOD vs. SUPPLY VOLTAGE
MAX6746
toc11
VCC (V)
TIMEOUT
PERIOD
(ms)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
6.5
7.0
7.5
8.0
8.5
9.0
6.0
1.5
6.0
CSWT = CSRT = 1500pF
RESET
WATCHDOG
Pin Description
PIN
MAX6746
MAX6747
MAX6748–
MAX6751
MAX6752
MAX6753
NAME
FUNCTION
1—
MR
Manual Reset Input. Pull MR low to manually reset the device. Reset
remains asserted for the reset timeout period after MR is released.
1
RESET IN
Reset Input. High-impedance input to the adjustable reset comparator.
Connect RESET IN to the center point of an external resistor-divider to
set the threshold of the externally monitored voltage.
1
SET0
Logic Input. SET0 selects watchdog window ratio or disables the
watchdog timer. See Table 1.
2
SWT
Watchdog Timeout Input.
MAX6746–MAX6751: Connect a capacitor between SWT and ground to
set the basic watchdog timeout period (tWD). Determine the period by
the formula tWD = 5.06 x 10
6 x CSWT with tWD in seconds and CSWT in
Farads. Extend the basic watchdog timeout period by using the WDS
input. Connect SWT to ground to disable the watchdog timer function.
MAX6752/MAX6753: Connect a capacitor between SWT and ground to
set the slow watchdog timeout period (tWD2). Determine the slow
watchdog period by the formula: tWD2 = 0.65 x 10
9 x CSWT with tWD2 in
seconds and CSWT in Farads. The fast watchdog timeout period is set
by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to
disable the watchdog timer function.) See Table 1.
3
SRT
Reset Timeout Input. Connect a capacitor from SRT to GND to select
the reset timeout period. Determine the period as follows: tRP = 5.06 x
10
6 x CSRT with tRP in seconds and CSRT in Farads.
4
GND
Ground
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