參數(shù)資料
型號: MAX6736XKTWD7+T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Low-Power Dual-/Triple-Voltage SC70 µP Supervisory Circuits
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
封裝: EIAJ, SC-70, 5 PIN
文件頁數(shù): 15/16頁
文件大小: 236K
代理商: MAX6736XKTWD7+T
MAX6736–MAX6745
Low-Power Dual-/Triple-Voltage SC70 P
Supervisory Circuits
8
_______________________________________________________________________________________
Pin Description
PIN
MAX6736
MAX6737
MAX6738
MAX6739
MAX6740
MAX6743
MAX6741
MAX6744
MAX6742
MAX6745
NAME
FUNCTION
11111
RESET
Reset Output, Push-Pull or Open Drain Active Low.
RESET
changes from high to low when any monitored power-supply
input (VCC1, VCC2, RSTIN) drops below its selected reset
threshold. It remains low until all monitored power-supply
inputs exceed their selected reset thresholds for the VCC
reset timeout period.
RESET is forced low if MR is low for at
least the
MR minimum input pulse width. It remains low for
the
MR reset timeout period after MR goes high. The push-
pull output is referenced to VCC1. The MAX6736/MAX6738
open-drain outputs require an external pullup resistor. The
MAX6740/MAX6741/MAX6742 open-drain outputs have an
internal 50k
pullup resistor to VCC1 and provide a manual
reset function.
22222
GND
Ground
33
———
MR
Manual Reset, Active Low. Pull low for at least
MR minimum
input pulse width to force
RESET low. Reset remains active
as long as
MR is low and for the MR reset timeout period
after
MR goes high. There is an internal 1.5k
pullup resistor
to VCC1.
4
44
VCC2
Voltage Input 1. Power supply and input for the secondary
P voltage reset monitor.
43
——
RSTIN
Adjustable Reset Threshold Input.
RESET is asserted when
RSTIN is below the internal 0.488V reference level. Set the
adjustable reset threshold with an external resistor-divider
network. Connect RSTIN to VCC1 if unused.
55555
VCC1
Voltage Input 2. Power supply and input for the primary P
voltage reset monitor.
————
4
PFI
Power-Fail Comparator Input.
PFO is asserted when PFI is
below 0.488V.
PFO is deasserted without any reset timeout
period when PFI goes above 0.488V. Connect PFI to an
external resistor network to set the desired monitor
threshold.
————
3
PFO
Power-Fail Comparator Output, Open Drain Active Low.
PFO
is asserted when PFI is below 0.488V.
———
3
POK1
VCC1 Power-OK Output, Open Drain Active High. POK1
remains low as long as VCC1 is below VTH1. POK1 output
goes high after VCC1 exceeds VTH1 for the POK1 timeout
period. POK1 logic is independent of the
MR or VCC2 inputs.
The output can be used to control VCC1-to-VCC2 supply
sequencing.
相關(guān)PDF資料
PDF描述
MAX6737XKSFD3+T Low-Power Dual-/Triple-Voltage SC70 µP Supervisory Circuits
MAX6744XKTZD3+T Low-Power Dual-/Triple-Voltage SC70 µP Supervisory Circuits
MAX6736XKTWD7+ Low-Power Dual-/Triple-Voltage SC70 µP Supervisory Circuits
MAX6746KA16+T µP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay
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