參數(shù)資料
型號: MAX6725KARYD1-T
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: Dual/Triple Ultra-Low-Voltage SOT23 &#181.P Supervisory Circuits
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
封裝: SOT-23, 8 PIN
文件頁數(shù): 4/19頁
文件大小: 324K
代理商: MAX6725KARYD1-T
MAX6715–MAX6729
Monitoring an Additional Power Supply
These P supervisors can monitor either positive or
negative supplies using a resistor voltage-divider to
PFI. PFO can be used to generate an interrupt to the P
or cause reset to assert (Figure 3).
Monitoring a Negative Voltage
The power-fail comparator can be used to monitor a
negative supply voltage using the circuit shown in
Figure 3. When the negative supply is valid, PFO is low.
When the negative supply voltage drops, PFO goes
high. The circuit’s accuracy is affected by the PFI
threshold tolerance, VCC, R1, and R2.
Negative-Going VCC Transients
The MAX6715–MAX6729 supervisors are relatively
immune to short-duration negative-going VCC transients
(glitches). It is usually undesirable to reset the P when
VCC experiences only small glitches. The Typical
Operating Characteristics show Maximum Transient
Duration vs. Reset Threshold Overdrive, for which reset
pulses are not generated. The graph was produced
using negative-going VCC pulses, starting above VTH
and ending below the reset threshold by the magnitude
indicated (reset threshold overdrive). The graph shows
the maximum pulse width that a negative-going VCC
transient may typically have without causing a reset
pulse to be issued. As the amplitude of the transient
increases (i.e., goes farther below the reset threshold),
the maximum allowable pulse width decreases. A 0.1F
bypass capacitor mounted close to the VCC pin pro-
vides additional transient immunity.
Watchdog Software Considerations
Setting and resetting the watchdog input at different
points in the program, rather than “pulsing” the watch-
dog input high-low-high or low-high-low, helps the
watchdog timer to closely monitor software execution.
This technique avoids a “stuck” loop where the watch-
dog timer continues to be reset within the loop, keeping
the watchdog from timing out. Figure 6 shows an exam-
ple flow diagram where the I/O driving the watchdog
input is set high at the beginning of the program, set low
at the beginning of every subroutine or loop, then set
high again when the program returns to the beginning. If
the program should “hang” in any subroutine, the I/O is
continually set low and the watchdog timer is allowed to
time out, causing a reset or interrupt to be issued.
Chip Information
TRANSISTOR COUNT: 1072
PROCESS: BiCMOS
Dual/Triple Ultra-Low-Voltage SOT23 P
Supervisory Circuits
12
______________________________________________________________________________________
MAX6728/
MAX6729
VEXT
R1
R3
R2
PFI
GND
PFO
A
VGOOD = DESIRED VEXT GOOD VOLTAGE THRESHOLD
VFAIL = DESIRED VEXT FAIL VOLTAGE THRESHOLD
VOH = VCC1 (FOR PUSH-PULL PFO)
R2 = 200k
(FOR > 2.5A R2 CURRENT)
R1 = R2 ((VGOOD - VPFI) - (VPFI)(VGOOD - VFAIL) / VOH) / VPFI
R3 = (R1 x VOH) / (VGOOD - VFAIL)
VGOOD
VFAIL
VIN
PFO
Figure 5. Adding Hysteresis to Power-Fail for Push-Pull PFO
START
SET WDI
HIGH
PROGRAM
CODE
SUBROUTINE OR
PROGRAM LOOP
SET WDI LOW
RETURN
SUBROUTINE
COMPLETED
HANG IN
SUBROUTINE
Figure 6. Watchdog Flow Diagram
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