參數(shù)資料
型號: MAX6692YMSA+
廠商: Maxim Integrated
文件頁數(shù): 8/16頁
文件大?。?/td> 194K
描述: IC SENSOR REMOTE SMBUS 8SOIC
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 100
功能: 溫度監(jiān)控系統(tǒng)(傳感器)
傳感器類型: 內部和外部
感應溫度: 0°C ~ 125°C,外部傳感器
精確度: ±3°C(最小值)
拓撲: ADC,多路復用器,寄存器庫
輸出類型: I²C?/SMBus?
輸出警報:
輸出風扇:
電源電壓: 3 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC(窄型)
包裝: 管件
Precision SMBus-Compatible Remote/Local
Temperature Sensors with Overtemperature Alarms
8  _______________________________________________________________________________________________________________________________________________________________  _______________
SMBCLK
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
A
B
C
D
E    F
G
H
I
J
SMBDATA
t
SU:STA
t
HD:STA
t
LOW
t
HIGH
t
SU:DAT
t
SU:STO
t
BUF
L
M
K
E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE
H = LSB OF DATA CLOCKED INTO SLAVE
I = MASTER PULLS DATA LINE LOW
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 3. SMBus Read Timing Diagram
Alarm Threshold Registers
Four registers store ALERT threshold valuesone high-
temperature (T
HIGH
) and one low-temperature (T
LOW
)
register each for the local and remote channels. If
either measured temperature equals or exceeds the
corresponding ALERT threshold value, the ALERT inter-
rupt asserts.
The power-on-reset (POR) state of both ALERT T
HIGH
registers is full scale (0101 0101, or +85癈). The POR
state of both T
LOW
registers is 0000 0000, or 0癈.
Two additional registers store remote and local alarm
threshold data corresponding to the OVERT output. The
values stored in these registers are high-temperature
thresholds. If either of the measured temperatures
equals or exceeds the corresponding alarm threshold
value, an OVERT output asserts. The POR state of the
OVERT threshold is 0110 1110 or +110癈 for the
MAX6648, and 0101 0101 or +85癈 for the MAX6692.
Diode Fault Alarm
A continuity fault detector at DXP detects an open cir-
cuit between DXP and DXN, or a DXP short to V
CC
,
GND, or DXN. If an open or short circuit exists, the
external temperature register is loaded with 1000 0000.
If the fault is an open-circuit fault bit 2 (OPEN) of the
status byte, it is set to 1 and the ALERT condition is
activated at the end of the conversion. Immediately
after POR, the status register indicates that no fault is
present. If a fault is present upon power-up, the fault is
not indicated until the end of the first conversion.
ALERT Interrupts
The ALERT interrupt occurs when the internal or exter-
nal temperature reading exceeds a high- or low-tem-
perature limit (user programmed) or when the remote
diode is disconnected (for continuity fault detection).
The ALERT interrupt output signal is latched and can
be cleared only by either reading the status register or
by successfully responding to an alert response
address. In both cases, the alert is cleared only if the
fault condition no longer exists. Asserting ALERT does
not halt automatic conversion. The ALERT output pin is
open drain, allowing multiple devices to share a com-
mon interrupt line.
The MAX6648/MAX6692 respond to the SMBus alert
response address, an interrupt pointer return-address
feature (see the Alert Response Address section). Prior
to taking corrective action, always check to ensure that
an interrupt is valid by reading the current temperature.
Fault Queue Register
In some systems, it may be desirable to ignore a single
temperature measurement that falls outside the ALERT
limits. Bits 2 and 3 of the fault queue register (address
22h) determine the number of consecutive temperature
faults necessary to set ALERT (see Tables 3 and 4).
Alert Response Address
The SMBus alert response interrupt pointer provides
quick fault identification for simple slave devices that
lack the complex, expensive logic needed to be a bus
master. Upon receiving an ALERT interrupt signal, the
host master can broadcast a receive byte transmission
to the alert response slave address (0001 100).
Following such a broadcast, any slave device that gen-
erated an interrupt attempts to identify itself by putting
its own address on the bus.
The alert response can activate several different slave
devices simultaneously, similar to the I
2
C general call. If
more than one slave attempts to respond, bus arbitration
rules apply, and the device with the lower address
code wins. The losing device does not generate an
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