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參數(shù)資料
| 型號(hào)： | MAX6689UP9A+T |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 7-Channel Precision Temperature Monitor |
| 中文描述： | 7-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | 4.40 MM, LEAD FREE, MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 240K |
| 代理商： | MAX6689UP9A+T |
MAX6689
7-Channel Precision Temperature Monitor
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +5.5V, VSTBY = VCC, TA = -40°C to +125°C, unless otherwise noted. Typical values are at VCC = +3.3V and TA =
+25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SMBus INTERFACE (SCL, SDA),
STBY
Logic-Input Low Voltage
VIL
0.8
V
VCC = 3.0V
2.2
Logic-Input High Voltage
VIH
VCC = 5.0V
2.4
V
Input Leakage Current
-1
+1
A
Output Low Voltage
VOL
ISINK = 6mA
0.3
V
Input Capacitance
CIN
5pF
SMBus-COMPATIBLE TIMING (Figures 3 and 4) (Note 2)
Serial-Clock Frequency
fSCL
(Note 3)
400
kHz
fSCL = 100kHz
4.7
Bus Free Time Between STOP
and START Condition
tBUF
fSCL = 400kHz
1.6
s
fSCL = 100kHz
4.7
START Condition Setup Time
fSCL = 400kHz
0.6
s
90% of SCL to 90% of SDA,
fSCL = 100kHz
0.6
Repeat START Condition Setup
Time
tSU:STA
90% of SCL to 90% of SDA,
fSCL = 400kHz
0.6
s
START Condition Hold Time
tHD:STA
10% of SDA to 90% of SCL
0.6
s
90% of SCL to 90% of SDA,
fSCL = 100kHz
4
STOP Condition Setup Time
tSU:STO
90% of SCL to 90% of SDA,
fSCL = 400kHz
0.6
s
10% to 10%, fSCL = 100kHz
1.3
Clock-Low Period
tLOW
10% to 10%, fSCL = 400kHz
1.3
s
Clock-High Period
tHIGH
90% to 90%
0.6
s
fSCL = 100kHz
300
Data Hold Time
tHD:DAT
fSCL = 400kHz (Note 4)
900
ns
fSCL = 100kHz
250
Data Setup Time
tSU:DAT
fSCL = 400kHz
100
ns
fSCL = 100kHz
1
Receive SCL/SDA Rise Time
tR
fSCL = 400kHz
0.3
s
Receive SCL/SDA Fall Time
tF
300
ns
Pulse Width of Spike Suppressed
tSP
050
ns
SMBus Timeout
tTIMEOUT
SDA low period for interface reset
25
37
45
ms
Note 1: All parameters are tested at TA = +85°C. Specifications over temperature are guaranteed by design.
Note 2: Timing specifications are guaranteed by design.
Note 3: The serial interface resets when SCL is low for more than tTIMEOUT.
Note 4: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SCL’s falling edge.
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