參數(shù)資料
型號: MAX6660AEE+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調(diào)理
英文描述: Remote-Junction Temperature-Controlled Fan-Speed Regulator with SMBus Interface
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 15/21頁
文件大?。?/td> 271K
代理商: MAX6660AEE+
MAX6660
Remote-Junction Temperature-Controlled
Fan-Speed Regulator with SMBus Interface
_______________________________________________________________________________________
3
Note 1: Junction Temperature = TA. This implies zero dissipation in pass transistor (no load, or fan turned off).
Note 2: TRJ, Remote Temperature accuracy is guaranteed by design, not production tested.
Note 3: Guaranteed by design. Not production tested.
Note 4: The MAX6660 includes an SMBus timeout, which resets the interface whenever SMBCLK or SMBDATA has been low for
greater than 25ms. This feature can be disabled by setting bit 2 of the Fan Gain register at 16h/1Bh to a 1. When the timeout
is disabled, the minimum clock frequency is DC.
Note 5: Note that a transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of
SMBCLK’s falling edge.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3V to +5.5V, VVFAN = +12V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = +3.3V and
TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tach Input Transition Level
VVFAN = 12V
10.5
V
Tach Input Hysteresis
VFAN = 12V
190
mV
Current-Sense Tach Threshold
20
mA
Current-Sense Tach Hysteresis
0.3
mA
Fan Output Current
250
mA
Fan Output Current Limit (Note 3)
320
410
mA
Fan Output On-Resistance
RONF
250mA load
4
SMBus INTERFACE: SMBDATA, ALERT, STBY, OVERT
Logic Input Low Voltage
VIL
VCC = +3.0V to +5.5V
0.8
V
VCC = +3.0V
2.2
Logic Input High Voltage
VIH
VCC = +5.5V
2.6
V
Input Leakage Current
I_leak
VIN = GND or VCC
-2
+2
A
Output Low Sink Current
IOL
VOL = 0.4V
6
mA
Input Capacitance
Cin
5pF
Output High Leakage Current
VOH = 5.5V
1
A
Serial Clock Frequency
fSCL
(Note 4)
0
100
kHz
Bus Free Time Between Stop
and Start Conditions
tBUF
4.7
s
Start Condition Setup Time
4.7
s
Repeat Start Condition Setup
Time
tSU:STA
90% to 90%
50
s
Start Condition Hold Time
tHD:STA
10% of SMBDATA to 90% of SMBCLK
4
s
Stop Condition Setup Time
tSU:STO
90% of SMBCLK to 10% of SMBDATA
4
s
Clock Low Time
tLOW
10% to 10%
4.7
s
Clock High Time
tHIGH
90% to 90%
4
s
Data Setup Time
tSU:DAT
90% of SMBDATA to 10% of SMBCLK
250
ns
Data Hold Time
tHD:DAT
(Note 5)
0
s
Receive SMBCLK/SMBDATA
Rise Time
tR
1s
Receive SMBCLK/SMBDATA
Fall Time
tF
300
ns
SMBus Timeout
tTIMEOUT
SMBDATA and SMBCLK time low for reset
of serial interface
25
40
ms
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