PECI-to-I2C Translator 13 Maxim Integrated The MAX6618 SCL and SDA lines " />
參數(shù)資料
型號: MAX6618AUB+TG11
廠商: Maxim Integrated Products
文件頁數(shù): 5/17頁
文件大?。?/td> 0K
描述: IC TRANSLATOR PECI-I2C 10-MSOP
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
邏輯功能: 變換器
位數(shù): 1
輸入類型: PECL
輸出類型: I²C?
通道數(shù): 1
輸出/通道數(shù)目: 1
差分 - 輸入:輸出: 無/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -20°C ~ 120°C
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 10-µMAX
包裝: 帶卷 (TR)
MAX6618
PECI-to-I2C Translator
13
Maxim Integrated
The MAX6618 SCL and SDA lines operate as both
inputs and open-drain outputs. A pullup resistor is
required on SCL and SDA.
Each transmission consists of a START condition sent
by a master, followed by the MAX6618 7-bit slave
address, plus an R/W bit, one or more data bytes, and
finally a STOP condition (Figure 6). To write to a
MAX6618 register, a write transmission consists of a
START condition, followed by the MAX6618 7-bit slave
address plus R/W = 0, a register address byte, one
data byte, and finally a STOP condition. To read from a
MAX6618 register, a combined write and read trans-
missions are required. The first write transmission con-
sists of a START condition, followed by the MAX6618
7-bit slave address plus R/W = 0, a register address
byte, and finally a STOP condition that sets the register
to be read. The second read transmission consists of a
START condition, followed by the MAX6618 7-bit slave
address plus R/W = 1, one or more data bytes, and
finally a STOP condition that reads the data from the
specified register. These write and read transmissions
must be joined using a repeated START without a
STOP after the write transaction, even though the
MAX6618 7-bit slave address needs to be present pre-
ceding the R/W bits.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 6).
SDA
SCL
START
CONDITION
STOP
CONDITION
S
P
Figure 6. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 7. Bit Transfer
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