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參數(shù)資料
| 型號： | MAX6324_UT__-T |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | レP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset |
| 中文描述： | レP監(jiān)控電路與窗口（最小/最大）看門狗和手動復(fù)位 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 226K |
| 代理商： | MAX6324_UT__-T |
Interfacing to μPs with
Bidirectional Reset Pins
Since the
RESET
output on the MAX6324 is open-drain,
this device easily interfaces with μPs that have bidirec-
tional reset pins, such as the Motorola 68HC11.
Connecting the μP supervisor’s
RESET
output directly
to the microcontroller’s (μC’s)
RESET
pin with a single
pullup resistor allows either device to assert reset
(Figure 7).
MAX6324 Open-Drain
RESET
Output
Allows Use with Multiple Supplies
Generally, the pullup resistor connected to the
MAX6324 will connect to the supply voltage that is
being monitored at the IC’s V
CC
pin. However, some
systems may use the open-drain output to level-shift
from the monitored supply to reset circuitry powered by
some other supply (Figure 8). Keep in mind that as the
MAX6324’s V
CC
decreases below
+
1.2V, so does the
IC’s ability to sink current at
RESET.
Also, with any pull-
up resistor,
RESET
will be pulled high as V
CC
decays
toward 0. The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
Watchdog Software Considerations
To help the watchdog timer monitor software execution
more closely, set and reset the watchdog input at dif-
ferent points in the program, rather than “pulsing” the
watchdog input high-low-high or low-high-low. This
technique avoids a “stuck” loop in which the watchdog
time would continue to be reset within the loop, keeping
the watchdog from timing out.
Figure 9 shows an example of a flow diagram where
the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
every subroutine or loop, then set high again when the
program returns to the beginning. If the program should
“hang” in any subroutine, the problem would be quickly
corrected, since the I/O is continually set low and the
watchdog time is allowed to time out, causing a reset or
interrupt to be issued.
WDPO
to
MR
Loopback
An error detected by the watchdog often indicates that
a problem has occurred in the μP code execution. This
could be a stalled instruction or a loop from which the
processor cannot free itself. If the μP will still respond to
a nonmaskable input (NMI), the processor can be redi-
rected to the proper code sequence by connecting the
WDPO
output to an NMI input. Internal RAM data
should not be lost, but it may have been contaminated
by the same error that caused the watchdog to time
out.
If the processor will not recognize NMI inputs, or if the
internal data is considered potentially corrupted when a
watchdog error occurs, the processor should be
restarted with a reset function. To obtain proper reset
timing characteristics, the
WDPO
output should be con-
nected to the
MR
input, and the
RESET
output should
M
μP Supervisory Circuits with Windowed
(Min/Max) Watchdog and Manual Reset
_______________________________________________________________________________________
9
MAX6323
GND
V
CC
V
CC
RESET
R1
100k
Figure 6.
RESET
Valid to V
CC
= Ground Circuit
MAX6324
GND
GND
V
CC
V
CC
V
CC
μ
P
RESET
RESET
INPUT
Figure 7. Interfacing to μPs with Bidirectional Reset Pins
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