參數(shù)資料
型號: MAX5972AETE+T
廠商: Maxim Integrated
文件頁數(shù): 3/13頁
文件大小: 1120K
描述: IC CONTROLLER INTERFACE 16TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 以太網(wǎng)供電開關(guān)(PoE)
應(yīng)用: IP 電話,LAN 網(wǎng)絡(luò)供電,網(wǎng)絡(luò)路由器和交換機(jī)
內(nèi)部開關(guān):
電流限制: 可調(diào)
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(5x5)
包裝: 帶卷 (TR)
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
 = (V
DD
 - V
SS
) = 48V, R
DET
 = 24.9k? R
CLS
 = 615? RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to V
SS,
 
unless otherwise noted. T
A
 = T
J
 = -40NC to +85NC, unless otherwise noted. Typical values are at T
A
 = +25NC.) (Note 3)
Note 3: This device is 100% production tested at T
A
 = +25NC. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between V
DD
 and V
SS
. See Figure 1.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage that takes V
DD
 below V
ON
 shorter than or equal to t
OFF_DLY
 does not cause the MAX5972A
to exit power-on mode.
Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload
condition across V
DD
 and RTN.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
 Turn-On Voltage
V
ON
V
IN
 rising
34.3
35.4
36.6
V
V
IN
 Turn-Off Voltage
V
OFF
V
IN
 falling
30
V
V
IN
 Turn-On/-Off Hysteresis
V
HYST_UVLO
(Note 7)
4.2
V
V
IN
 Deglitch Time
t
OFF_DLY
V
IN
 falling from 40V to 20V (Note 8)
30
120
Fs
Inrush to Operating Mode
Delay
t
DELAY
t
DELAY
 = minimum PG current pulse width
after entering into power mode
80
96
112
ms
Isolation Power MOSFET
On-Resistance
R
ON_ISO
I
RTN
 = 600mA
T
J
 = +25NC
0.7
1.1
I
T
J
 = +85NC
0.9
1.5
T
J
 = +125NC
1.15
RTN Leakage Current
I
RTN_LKG
V
RTN
 = 12.5V to 30V
10
FA
CURRENT LIMIT
Inrush Current Limit
I
INRUSH
During initial turn-on period,
V
RTN
 = 1.5V
90
135
180
mA
Current Limit During Normal
Operation
I
LIM
After inrush completed,
V
RTN
 = 1V
720
800
880
mA
Foldback Threshold
V
RTN
(Note 9)
13
16.5
V
LOGIC
WAD Detection Threshold
V
WAD-REF
V
WAD
 rising, V
IN
 = 14V to 48V (referenced
to RTN)
8
9
10
V
WAD Detection Threshold
Hysteresis
V
WAD
 falling, V
RTN
 = 0V, V
SS
 
unconnected
0.725
WAD Input Current
I
WAD-LKG
V
WAD
 = 10V (referenced to RTN)
3.5
FA
2EC Sink Current
V
2EC
 = 3.5V (referenced to RTN), V
SS
 
unconnected
1
1.5
2.25
mA
2EC Off-Leakage Current
V
2EC
= 48V
1
FA
PG Sink Current
V
RTN
 = 1.5V, V
PG
= 0.8V, during inrush
period
125
230
375
FA
PG Off-Leakage Current
V
PG
 = 60V
1
FA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
T
SD
T
J
 rising
+140
NC
Thermal-Shutdown Hysteresis
T
J
 falling
+28
NC
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