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參數(shù)資料
| 型號： | MAX5960AECS+T |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 632K |
| 描述： | IC CTRLR HOT-PLUG QD 80-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用型，PCI Express? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 3.3V，12V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP |
| 供應(yīng)商設(shè)備封裝： | 80-TQFP（12x12） |
| 包裝： | 帶卷 (TR) |
Quad PCI Express, Hot-Plug Controllers
______________________________________________________________________________________ 11
Pin Description
PIN
NAME
FUNCTION
1
12SB-
Slot B 12V Negative Current-Sense Input. Connect 12SB- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
2
12SB+
Slot B 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor to
12SB+ using the Kelvin-sensing technique to ensure accurate current sensing.
3
AUXONB
Slot B 3.3V Auxiliary Output Enable. A logic-high at AUXONB turns on the slot B auxiliary output.
4
ONB
Slot B 12V and 3.3V Main Outputs Enable. A logic-high at ONB turns on the 12V and 3.3V main outputs
of slot B (see Table 2).
5
INPUT1
Digital Logic Gate Input 1
6
OUTPUT1 Digital Output 1. 4ms debounced digital output of INPUT1.
7
INPUT2
Digital Logic Gate Input 2
8
OUTPUT2 Digital Output 2. 4ms debounced digital output of INPUT2.
9, 61, 80
N.C.
No Connection. Not internally connected. Leave unconnected.
10
FOND
Slot D Forced-On Input. FOND has a 50k?internal pullup to 3.3VAUXIN. A logic-low on FOND turns on
all slot D outputs as long as the power inputs are within their operating range, regardless of the status
of the other input signals. Leave FOND unconnected for normal operation.
11
PRES-DETD
Slot D Present-Detect Input. PRES-DETD accepts inputs from PRSNT#_# on a PCIe connector. PRES-
DETD has an internal 50k?pullup to 3.3VAUXIN. When PRES-DETA is low, the outputs follow the
command from OND and AUXOND after a 4ms debounced time. When PRES-DETD goes from low to
high, all outputs of the respective slot shut down with no delay.
12
OND
Slot D 12V and 3.3V Main Outputs Enable. A logic-high at OND turns on the 12V and 3.3V main outputs
of slot D (see Table 2).
13
AUXOND
Slot D 3.3V Auxiliary Output Enable. A logic-high at AUXOND turns on the slot D auxiliary output.
14
GND
Ground
15
FONC
Slot C Forced-On Input C. FONC has a 50k?internal pullup to 3.3VAUXIN. A logic-low on FONC turns
on all slot C outputs as long as the power inputs are within their operating range, regardless of the
status of the other input signals. Leave FONC unconnected for normal operation.
16
PRES-DETC
Slot C Present-Detect Input. PRES-DETC accepts inputs from PRSNT#_# on a PCIe connector. PRES-
DETC has an internal 50k?pullup to 3.3VAUXIN. When PRES-DETC is low, the outputs follow the
command from ONC and AUXONC after a 4ms debounced time. When PRES-DETC goes from low to
high, all outputs of the respective slot shut down with no delay.
17
ONC
Slot C 12V And 3.3V Main Outputs Enable. A logic-high at ONC turns on the 12V and 3.3V main outputs
of slot C (see Table 2).
18
AUXONC
Slot C 3.3V Auxiliary Output Enable. A logic-high at AUXONC turns on the slot C auxiliary output.
19
12SC+
Slot C 12V Positive Current-Sense Input. Connect the positive terminal of the current-sense resistor to
12SC+ using the Kelvin-sensing technique to ensure accurate current sensing.
20
12SC-
Slot C 12V Negative Current-Sense Input. Connect 12SC- to the negative side of the current-sense
resistor using the Kelvin-sensing technique to ensure accurate current sensing.
21
12GC
Slot C 12V Gate-Drive Output. Connect 12GC to the gate of slot Cs 12V MOSFET. At power-up, 12GC
is raised to the internal charge-pump voltage level by a constant current.
22
3.3SC+
Slot C 3.3V Positive Current-Sense Input. Connect the positive side of the current-sense resistor to
3.3SC+ using the Kelvin-sensing technique to ensure accurate current sensing.
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