參數(shù)資料
型號(hào): MAX5952CUAX+
廠(chǎng)商: Maxim Integrated
文件頁(yè)數(shù): 31/50頁(yè)
文件大小: 1006K
描述: IC PSE CNTRLR FOR POE 36-SSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類(lèi)型: 以太網(wǎng)供電控制器(PoE)
應(yīng)用: 遠(yuǎn)程外設(shè)(工業(yè)控制,相機(jī),數(shù)據(jù)訪(fǎng)問(wèn))
內(nèi)部開(kāi)關(guān): 無(wú)
工作溫度: 0°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 管件
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
______________________________________________________________________________________   31
PGOOD_ is set to 1 (Table 14) at the end of the power-
up startup period if the power-good condition is met (0
< (V
OUT
- V
EE
) < PG
TH
). The power-good condition
must remain valid for more than t
PGOOD
to assert
PGOOD_. PGOOD_ is reset to 0 whenever the output
falls out of the power-good condition. A fault condition
immediately forces PGOOD_ low.
PWR_EN_ is set to 1 when the port power is turned on.
PWR_EN resets to 0 as soon as the port turns off. Any
transition of PGOOD_ and PWR_EN_ bits set the corre-
sponding bit in the power event registers R02h/R03h
(Table 8). A reset sets R10h = 00h.
Table 14. Power Status Register
ADDRESS = 10h
SYMBOL
BIT
R/W
DESCRIPTION
PGOOD4
7
R
Power-good condition on port 4
PGOOD3
6
R
Power-good condition on port 3
PGOOD2
5
R
Power-good condition on port 2
PGOOD1
4
R
Power-good condition on port 1
PWR_EN4
3
R
Power is enabled on port 4
PWR_EN3
2
R
Power is enabled on port 3
PWR_EN2
1
R
Power is enabled on port 2
PWR_EN1
0
R
Power is enabled on port 1
Table 15. Address Input Status Register
ADDRESS = 11h
SYMBOL
BIT
R/W
DESCRIPTION
Reserved
7
R
Reserved
Reserved
6
R
Reserved
A3
5
R
Device address, A3 pin latched-in status
A2
4
R
Device address, A2 pin latched-in status
A1
3
R
Device address, A1 pin latched-in status
A0
2
R
Device address, A0 pin latched-in status
MIDSPAN
1
R
MIDSPAN inputs latched-in status
AUTO
0
R
AUTO inputs latched-in status
A3, A2, A1, A0 (Table 15) represent the four LSBs of
the MAX5952 address (Table 4). During a reset, the
device latches into R11h. These four bits address from
the corresponding inputs as well as the state of the
MIDSPAN and AUTO inputs. Changes to those inputs
during normal operation are ignored.
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