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鍨嬭櫉锛� MAX5945EAX+T
寤犲晢锛� Maxim Integrated Products
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鎻忚堪锛� IC NETWORK PWR CTRL 36-SSOP
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯欐簴鍖呰锛� 1,000
鎺у埗鍣ㄩ鍨嬶細 缍�(w菐ng)绲￠浕婧愭帶鍒跺櫒
鎺ュ彛锛� I²C
闆绘簮闆诲锛� 3.3V
闆绘祦 - 闆绘簮锛� 4.2mA
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 36-BSOP锛�0.295"锛�7.50mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 36-SSOP
鍖呰锛� 甯跺嵎 (TR)
MOSFET Gate Driver
Connect the gate of the external n-channel MOSFET to
GATE_. An internal 50A current source pulls GATE_ to
(VEE + 10V) to turn on the MOSFET. An internal 40A
current source pulls down GATE_ to VEE to turn off the
MOSFET.
The pullup and pulldown current controls the maximum
slew rate at the output during turn-on or turn-off. The
pullup current (gate-charging current) is programmable
using R23h[5-7]. Use the following equation to set the
maximum slew rate:
where CGD is the total capacitance between GATE and
DRAIN of the external FET. Current limit and the capac-
itive load at the drain control the slew rate during start-
up. During current-limit regulation, the MAX5945
manipulates the GATE_ voltage to control the voltage at
SENSE_. A fast pulldown activates if SENSE_ over-
shoots the limit threshold. The fast pulldown current
increases with the amount of overshoot. The maximum
fast pulldown current is 100mA.
During turn-off, when the GATE voltage reaches a value
lower than 1.2V, a strong pulldown switch is activated
to keep the FET securely off.
Digital Logic
VDD supplies power for the internal logic circuitry. VDD
ranges from +1.71V to +3.7V and determines the logic
thresholds for the CMOS connections (SDAIN,
SDAOUT, SCL, AUTO, SHD_, A_). This voltage range
enables the MAX5945 to interface with a nonisolated
low-voltage microcontroller. The MAX5945 checks the
digital supply for compatibility with the internal logic.
The MAX5945 also features a VDD undervoltage lockout
(VDDUVLO) of +1.35V. A VDDUVLO condition keeps the
MAX5945 in reset and the ports shut off. Bit 0 in the
supply event register shows the status of VDDUVLO
(Table 11) after VDD has recovered. All logic inputs and
outputs reference to DGND. DGND and AGND are
completely isolated internally to the MAX5945. In a
completely isolated system, the digital signal can be
referenced indifferently to VAGND or VEE or at voltages
even higher than AGND (up to 60V). VDD - VDGND must
be greater than 3.0V when VDGND 鈮� (VEE + 3.0V)
When using the AC disconnect detection feature,
AGND must be connected directly to DGND and VDD
must be greater than +3V. In this configuration, con-
nect DGND to AGND at a single point in the system as
close to MAX5945 as possible.
Hardware Shutdown
SHD_ shuts down the respective ports without using
the serial interface. Hardware shutdown offers an emer-
gency turn-off feature that allows a fast disconnect of
the power supply from the port. Pull SHD_ low to
remove power.
Interrupt
The MAX5945 contains an open-drain logic output (INT)
that goes low when an interrupt condition exists. R00h
and R01h (Tables 5 and 6) contain the definitions of the
interrupt registers. The mask register R01h determines
events that trigger an interrupt. As a response to an
interrupt, the controller reads the status of the event reg-
ister to determine the cause of the interrupt and takes
subsequent actions. Each interrupt event register also
contains a clear-on-read (CoR) register. Reading
through the CoR register address clears the interrupt.
INT remains low when reading the interrupt through the
read-only addresses. For example, to clear a startup
fault on port 4 read address 09h (see Table 10). Use the
global pushbutton bit on register 1Ah (bit 7, Table 22) to
clear interrupts, or use a software or hardware reset.
Undervoltage and Overvoltage Protection
The MAX5945 contains several undervoltage and over-
voltage protection features. Table 11 in the Register Map
and Description section shows a detailed list of the
undervoltage and overvoltage protection features. An
internal VEE undervoltage lockout (VEEUVLO) circuit
keeps the MOSFET off and the MAX5945 in reset until
VAGND - VEE exceeds 29V for more than 3ms. An internal
VEE overvoltage (VEE_OV) circuit shuts down the ports
when (VAGND - VEE) exceeds 60V. The digital supply also
contains an undervoltage lockout (VDDUVLO).
V
t
I
C
OUT
GATE
GD
=
MAX5945
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________
17
Figure 4. Foldback Current Characteristics
50V
30V
VSU_LIM
VSU_LIM / 3
(VSENSE_ - VEE)
(VOUT_ - VEE)
鐩搁棞PDF璩囨枡
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鍙冩暩(sh霉)鎻忚堪
MAX5945EVKIT 鍔熻兘鎻忚堪:闆绘簮绠＄悊IC闁嬬櫦(f膩)宸ュ叿 Evaluation Kit/Evaluation System for the MAX5945 RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 鐢�(ch菐n)鍝�:Evaluation Kits 椤炲瀷:Battery Management 宸ュ叿鐢ㄤ簬瑭曚及:MAX17710GB 杓稿叆闆诲: 杓稿嚭闆诲:1.8 V
MAX5945EVSYS 鍔熻兘鎻忚堪:闆绘簮绠＄悊IC闁嬬櫦(f膩)宸ュ叿 Evaluation Kit/Evaluation System for the MAX5945 RoHS:鍚� 鍒堕€犲晢:Maxim Integrated 鐢�(ch菐n)鍝�:Evaluation Kits 椤炲瀷:Battery Management 宸ュ叿鐢ㄤ簬瑭曚及:MAX17710GB 杓稿叆闆诲: 杓稿嚭闆诲:1.8 V
MAX5946AETJ 鍒堕€犲晢:Maxim Integrated Products 鍔熻兘鎻忚堪:DUAL PCI-EXPRESS HOT-PLUG CONTROLLER - Rail/Tube
MAX5946AETX 鍔熻兘鎻忚堪:鐔辨彃鎷斿姛鐜囧垎甯� RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Controllers & Switches 闆绘祦闄愬埗: 闆绘簮闆诲-鏈€澶�:7 V 闆绘簮闆诲-鏈€灏�:- 0.3 V 宸ヤ綔婧害鑼冨湇: 鍔熺巼鑰楁暎: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Tube
MAX5946AETX+ 鍔熻兘鎻忚堪:鐔辨彃鎷斿姛鐜囧垎甯� Dual PCIe Hot-Plug Controller RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Controllers & Switches 闆绘祦闄愬埗: 闆绘簮闆诲-鏈€澶�:7 V 闆绘簮闆诲-鏈€灏�:- 0.3 V 宸ヤ綔婧害鑼冨湇: 鍔熺巼鑰楁暎: 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Tube
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