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參數(shù)資料
| 型號： | MAX5942BESE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/24頁 |
| 文件大小： | 0K |
| 描述： | IC IEEE 802.3AF POE SYSTM 16SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 控制器類型： | 以太網(wǎng)供電控制器（POE） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 48V |
| 電流 - 電源： | 1mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
MAX5942A/MAX5942B
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
______________________________________________________________________________________
13
MAX5942A/MAX5942B
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5942A/MAX5942B exhibit a cur-
rent characteristic with values indicated in Table 2. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur-
rent includes the current drawn by the 25.5k detection
signature resistor and the supply current of the
MAX5942A/MAX5942B so that the total current drawn by
the PD is within the IEEE 802.3af standard figures. The
classification current is turned off whenever the device is
in power mode.
Power Mode
During power mode, when VIN rises above the undervolt-
age lockout threshold (VUVLO,ON), the MAX5942A/
MAX5942B gradually turn on the internal N-channel MOS-
FET Q1 (see Figure 2). The MAX5942A/MAX5942B
charge the gate of Q1 with a constant current source
(10A, typ). The drain-to-gate capacitance of Q1 limits
the voltage rise rate at the drain of MOSFET, thereby limit-
ing the inrush current. To reduce the inrush current, add
external drain-to-gate capacitance (see the Inrush
Current section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5942A/MAX5942B assert the PGOOD/
PGOOD outputs. The MAX5942A/MAX5942B have a wide
UVLO hysteresis and turn-off deglitch time to compensate
for the high impedance of the twisted-pair cable.
Undervoltage Lockout
The MAX5942A/MAX5942B operate up to a 67V supply
voltage with a default UVLO turn-on set at 39V and a
UVLO turn-off set at 30V. Adjust the UVLO threshold
using a resistor-divider connected to UVLO (see Figure
3). When the input voltage is above the UVLO threshold
(VUVLO,ON), the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO thresh-
old (VUVLO,OFF) for more than tOFF_DLY, the MOSFET
turns off.
To adjust the UVLO threshold, connect an external
resistor-divider from GND to UVLO and from UVLO to
VEE. Use the following equations to calculate R1 and
R2 for a desired UVLO threshold:
R1 = 25.5k - R2
where VIN,EX is the desired UVLO threshold. Since the
resistor-divider replaces the 25.5k PD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5k
±1%. When using the external resistor-divider, the
MAX5942 has an external reference voltage hysteresis of
20% (typ). In other words, when UVLO is programmed
externally, the turn-off threshold will be 80% (typ) of the
new UVLO turn-on threshold.
Inrush Current Limit
The MAX5942A/MAX5942B charge the gate of the inter-
nal MOSFET with a constant current source (10A, typ).
The drain-to-gate capacitance of the MOSFET limits the
voltage rise rate at the drain, thereby limiting the inrush
current. Add an external capacitor from GATE to OUT
to further reduce the inrush current. Use the following
equation to calculate the inrush current:
The recommended inrush current for a PoE application
is 100mA.
PGOOD/
PGOOD Outputs
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when VOUT is within 1.2V
of VEE and when GATE is 5V above VEE. Otherwise,
PGOOD is pulled to VOUT (given that VOUT is at least 5V
below GND). Connect PGOOD to SS_SHDN to enable
the PWM controller.
PGOOD is an open-drain, active-low logic output.
PGOOD is pulled to VEE when VOUT is within 1.2V of VEE
and when GATE is 5V above VEE. Otherwise, PGOOD
goes high impedance.
II
x
C
INRUSH
G
OUT
GATE
=
Rk
x
V
REF UVLO
INEX
225 5
=
.
,
R1
UVLO
GND
VEE
R2
VIN = 24V TO 60V
MAX5942A
MAX5942B
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
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| MAX5943AEEE+ | 功能描述:熱插拔功率分布 FireWire Current Limiter RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5943AEEE+T | 功能描述:熱插拔功率分布 FireWire Current Limiter RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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