參數(shù)資料
型號: MAX5940CESA+T
廠商: Maxim Integrated Products
文件頁數(shù): 9/15頁
文件大?。?/td> 0K
描述: IC IEEE 802.3AF PD INTFC 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
控制器類型: 供電設(shè)備接口控制器(PD)
接口: IEEE 802.3af
電源電壓: 48V
電流 - 電源: 1mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________
3
Note 1:
All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.
Note 2:
The input offset current is illustrated in Figure 1.
Note 3:
Effective differential input resistance is defined as the differential resistance between GND and VEE without any external
resistance. See Figure 1.
Note 4:
Classification current is turned off whenever the IC is in power mode.
Note 5:
See Table 2 in the PD Classification Mode section. RDISC and RCL must be ±1%, 100ppm or better. ICLASS includes the IC
bias current and the current drawn by RDISC.
Note 6:
See the Thermal Dissipation section for details.
Note 7:
When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5k
Ω (±1%), the turn-
on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when VIN is at the maximum voltage (MAX5940B only).
Note 8:
When the UVLO input voltage is below VTH,G,UVLO, the MAX5940B sets the UVLO threshold internally.
Note 9:
An input voltage or VUVLO glitch below their respective thresholds shorter than or equal to tOFF_DLY does not cause the
MAX5940A/MAX5940B/MAX5940C/MAX5940D to exit power-on mode (as long as the input voltage remains above an opera-
ble voltage level of 12V).
Note 10: Guaranteed by design.
Note 11: PGOOD references to OUT while PGOOD references to VEE.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UVLO Input Ground Sense
Threshold (Note 8)
VTH,G,UVLO
50
440
mV
UVLO Input Ground Sense Glitch
Rejection
UVLO = VEE
7s
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time (Note 9)
tOFF_DLY
VIN, VUVLO falling
0.32
ms
TA = +25°C
(Note 10)
0.6
1.1
Isolation Switch N-Channel
MOSFET On-Resistance
RON
Output current =
300mA, VGATE = 6V,
measured between
OUT and VEE
TA = +85°C
0.8
1.5
Ω
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage
VGSTH
OUT = GND, VGATE - VEE, output current
< 1A
0.5
V
GATE Pulldown Switch Resistance
RG
Power-off mode, VIN = 12V,
UVLO = VEE for MAX5940B
38
80
Ω
GATE Charging Current
IG
VGATE = 2V
5
10
15
A
GATE High Voltage
VGATE
IGATE = 1A
5.59
5.76
5.93
V
VOUT - VEE, |VOUT - VEE| decreasing,
VGATE = 5.75V
1.16
1.23
1.31
V
PGOOD, PGOOD Assertion VOUT
Threshold
VOUTEN
Hysteresis
70
mV
(GATE - VEE) increasing, OUT = VEE
4.62
4.76
4.91
V
PGOOD, PGOOD Assertion VGATE
Threshold
VGSEN
Hysteresis
80
mV
PGOOD, PGOOD Output Low
Voltage (Note 11)
VOLDCDC
ISINK = 2mA; for PGOOD, OUT
(GND - 5V)
0.4
V
PGOOD Leakage Current (Note 11)
GATE = high, GND - VOUT = 67V
1
A
PGOOD Leakage Current (Note 11)
GATE = VEE, PGOOD - VEE = 67V
1
A
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (GND - VEE) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = VEE, TA = -40
°C to +85°C, unless otherwise noted.
Typical values are at TA = +25
°C. All voltages are referenced to VEE, unless otherwise noted.) (Note 1)
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