參數(shù)資料
型號(hào): MAX5940AESA+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 14/15頁(yè)
文件大?。?/td> 0K
描述: IC IEEE 802.3AF PD INTFC 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
控制器類(lèi)型: 供電設(shè)備接口控制器(PD)
接口: IEEE 802.3af
電源電壓: 48V
電流 - 電源: 1mA
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
MAX5940A/MAX5940B/MAX5940C/MAX5940D
To adjust the UVLO threshold (MAX5940B/MAX5940D
only), connect an external resistor-divider from GND to
UVLO and from UVLO to VEE. Use the following equations
to calculate R1 and R2 for a desired UVLO threshold:
R1 = 25.5k
Ω - R2
where VIN,EX is the desired UVLO threshold. Since the
resistor-divider replaces the 25.5k
Ω PD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5k
Ω
±1%. When using the external resistor-divider, the
MAX5940B/MAX5940D has an external reference volt-
age hysteresis of 20% (typ). When UVLO is pro-
grammed externally, the turn-off threshold is 80% (typ)
of the new UVLO threshold.
Rk
x
V
REF UVLO
IN EX
225 5
=
.
,
Ω
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
8
_______________________________________________________________________________________
R1
GND
UVLO
GND
(UVLO)
( ) MAX5940B.
GATE
R2
R3
MAX5940B
MAX5940D
CLASSIFICATION
RCLASS
(PGOOD)
6.8V
EN
REF
2.46V
200mV
VEE
VGATE
1.2V, REF
5V, REF
Q4
PGOOD
OUT
Q3
Q1
Q2
EN
20%
Figure 2. Block Diagram
R1
UVLO
GND
VEE
R2
VIN = 12V TO 67V
MAX5940B
MAX5940D
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
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