參數(shù)資料
型號: MAX5939EESA+
廠商: Maxim Integrated
文件頁數(shù): 15/18頁
文件大?。?/td> 386K
描述: IC HOT-SWAP CTRLR -48V 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 100
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: -20 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
-48V Hot-Swap Controllers with External
R
SENSE
and High Gate Pulldown Current
______________________________________________________________________________________   15
The lowest practical R
DS(ON)
, within budget constraints
and with values from 14m& to 540m&, are available at
100V breakdown.
Ensure that the temperature rise of Q1 junction is not
excessive at normal load current for the package select-
ed. Ensure that I
CB
current during voltage transients
does not exceed allowable transient-safe operating-area
limitations. This is determined from the SOA and tran-
sient-thermal-resistance curves in the Q1 manufacturers
data sheet.
Example 1:
I
LOAD
= 2.5A, efficiency = 98%, then V
DS
= 0.96V is
acceptable, or R
DS(ON)
d 384m& at operating temper-
ature is acceptable. An IRL520NS 100V NMOS with
R
DS(ON)
d 180m& and I
D(ON)
= 10A is available in
D
2
PAK. (A Vishay Siliconix SUD40N10-25 100V NMOS
with R
DS(ON)
d 25m& and I
D(ON)
= 40A is available in
DPAK but may be more costly because of a larger die
size).
Using the IRL520NS, V
DS
d 0.625V even at +80癈 so effi-
ciency e 98.6% at 80癈. P
D
d 1.56W and junction temper-
ature rise above case temperature would be 5癈 due to
the package ?/DIV>
JC
= 3.1癈/W thermal resistance. Of
course, using the SUD40N10-25 will yield an efficiency
greater than 99.8% to compensate for the increased cost.
If I
CB
is set to twice I
LOAD
, or 5A, V
DS
momentarily dou-
bles to d 1.25V. If C
OUT
= 4000礔, transient-line input
voltage is 36V, the 5A charging-current pulse is:
Entering the data sheet transient-thermal-resistance
curves at 1ms provides a ?/DIV>
JC
= 0.9癈/W. P
D
= 6.25W,
so t
JC
= 5.6癈. Clearly, this is not a problem.
Example 2:
I
LOAD
= 10A, efficiency = 98%, allowing V
DS
= 0.96V
but R
DS(ON)
d 96m&. An IRF530 in a D
2
PAK exhibits
R
DS(ON)
d 90m& at +25癈 and d 135m& at +80癈.
Power dissipation is 9.6W at +25癈 or 14.4W at +80癈.
Junction-to-case thermal resistance is 1.9癈/W, so the
junction temperature rise would be approximately 5癈
above the +25癈 case temperature. For higher efficien-
cy, consider IRL540NS with R
DS(ON)
d 44m&. This
allows ?nbsp = 99%, P
D
d  4.4W, and T
JC
= +4癈
(?/DIV>
JC
= 1.1癈/W) at +25癈.
Thermal calculations for the transient condition yield
I
CB
= 20A, V
DS
= 1.8V, t = 0.5ms, transient ?/DIV>
JC
=
0.12癈/W, P
D
= 36W and t
JC
= 4.3癈.
Layout Guidelines
Good thermal contact between the MAX5921/MAX5939
and the external MOSFET is essential for the thermal-
shutdown feature to operate effectively. Place the
MAX5921/MAX5939 as close as possible to the drain of
the external MOSFET and use wide circuit-board traces
for good heat transfer. See Figure 15 for an example of
recommended layout for Kelvin-sensing current
through a sense resistor on a PC board.
t
F x
V
A
ms
   
.
 
=
=
4000
1 25
5
1
?/DIV>
500祍 x 128
V
OL
V
SENSE
V
GATE
t
1
t
3H
t
5H
t
2L
t
4L
Figure 14. MAX5921A Overcurrent Fault Example
SENSE RESISTOR
HIGH-CURRENT PATH
MAX5921
MAX5939
SENSE V
EE
Figure 15. Recommended Layout for Kelvin-Sensing Current
Through Sense Resistor
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