參數(shù)資料
型號(hào): MAX5887EGK+TD
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 16/18頁(yè)
文件大小: 0K
描述: IC DAC 14BIT 3.3V 500MSPS 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
設(shè)置時(shí)間: 11ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 130mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 500M
MAX5887
3.3V, 14-Bit, 500Msps High Dynamic
Performance DAC with Differential LVDS Inputs
_______________________________________________________________________________________
7
Pin Description
PIN
NAME
FUNCTION
1
B1P
Data Bit 1
2
B1N
Complementary Data Bit 1
3
B0P
Data Bit 0
4
B0N
Complementary Data Bit 0
5–8, 23,
34–38
N.C.
No Connection. Do not connect to these pins. Do not tie these pins together.
9, 41, 60, 62
DGND
Digital Ground
10, 40, 61
DVDD
Digital Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1F capacitor to the nearest DGND.
11, 16
VCLK
Clock Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1F capacitor to the nearest CLKGND.
12, 15
CLKGND
Clock Ground
13
CLKP
Converter Clock Input. Positive input terminal for the LVDS-compatible differential converter clock.
14
CLKN
Complementary Converter Clock Input. Negative input terminal for the LVDS-compatible differential
converter clock.
17
PD
Power-Down Input. PD pulled high enables the DAC’s power-down mode. PD pulled low allows for
normal operation of the DAC. This pin features an internal pulldown resistor.
18, 24, 29,
30, 32
AVDD
Analog Supply Voltage. Accepts a supply voltage range of 3.135V to 3.465V. Bypass each pin with a
0.1F capacitor to the nearest AGND.
19, 25, 28,
31, 33, EP
AGND
Analog Ground. Exposed paddle (EP) must be connected to AGND.
20
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F capacitor
to AGND. Can be driven with an external reference source.
21
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For 20mA full-scale
output current, connect a 2k
resistor between FSADJ and DACREF.
22
DACREF
Return Path for the Current Set Resistor. For 20mA full-scale output current, connect a 2k
resistor
between FSADJ and DACREF.
26
IOUTN
Complementary DAC Output. Negative terminal for differential current output. The full-scale output
current range can be set from 2mA to 20mA.
27
IOUTP
DAC Output. Positive terminal for differential current output. The full-scale output current range can
be set from 2mA to 20mA.
39
SEL0
Mode Select Input SEL0. Set high to activate the segment shuffling function. Since this pin features an
internal pulldown resistor, it can be left open or pulled low to disable the segment-shuffling function.
See Segment Shuffling in the Detailed Description section for more information.
42
B13P
Data Bit 13 (MSB)
43
B13N
Complementary Data Bit 13 (MSB)
44
B12P
Data Bit 12
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