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參數(shù)資料
| 型號： | MAX5885EVKIT |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Evaluation Kit for the MAX5883/MAX5884/MAX5885 |
| 中文描述： | MAX5883、MAX5884、MAX5885評估板 |
| 文件頁數(shù)： | 5/14頁 |
| 文件大小： | 382K |
| 代理商： | MAX5885EVKIT |
E
MAX5858A Evaluation Kit
_______________________________________________________________________________________
5
Reference Voltage Options
The MAX5858A EV kit supports both internal and exter-
nal reference configurations. The internal reference
voltage can be accessed at the REFO pad. The EV kit
also accepts an external reference voltage at the REFO
pad to set the full-scale analog-output signal level.
Jumper JU5 selects the reference voltage options for
the EV kit. Table 5 lists the jumper selection.
Evaluating the MAX5858
The MAX5858A EV kit also evaluates the pin-compatible
MAX5858. Refer to the MAX5858 data sheet for more
details on the MAX5858 functions. To evaluate the
MAX5858, replace U1 with the MAX5858 and install a
shunt on jumper JU4.
Evaluating the MAX5856A
The MAX5858A EV kit also evaluates the MAX5856A.
Refer to the MAX5856A data sheet for more details on
the MAX5856A functions. To evaluate the MAX5856A,
the following component changes on the MAX5858A
EV kit are necessary:
Replace U1 with the MAX5856A.
Install a shunt on J1-3 and J1-4.
Install a shunt on J1-5 and J1-6.
Install a shunt on J1-23 and J1-24.
Install a shunt on J1-25 and J1-26.
See Tables 6 and 7 for the data bits of the
MAX5856A, with respect to header J1 on the
MAX5858A EV kit.
PLL Clock Multiplier (MAX5858A and
MAX5856A only)
The MAX5858A (10 bit) and MAX5856A (8 bit) feature a
PLL clock multiplier that generates and distributes all
internally synchronized high-speed clock signals
required by the input data latches, interpolation filters,
and DAC cores. Jumper JU4 sets the PLL clock multi-
plier options. Table 8 lists the jumper selection.
Clock
The MAX5858A EV kit features two input clock options: a
single-ended input clock applied to CLKIN or a differen-
tial clock applied to CLKD. When evaluating the
MAX5858A or the MAX5856A, CLKIN is used in PLL
enabled mode, and CLKD is used in PLL disabled
mode. The clock signal applied to the CLKIN SMA input
connector has to meet CMOS logic-level requirements.
When evaluating the MAX5858, only the CLKD SMA input
connector is used. Jumpers JU1, JU4, JU10, and JU11
set the input clock mode for the MAX5858A. Table 9 lists
the jumper configurations.
Table 6. MAX5856A Data Bits DA7 Through DA0 on the MAX5858A EV Kit
Table 8. PLL Clock Multiplier (Jumper
JU4) for MAX5858A and MAX5856A
CLOCK
MODE
JUMPER SETTINGS
CLKIN mode
MAX5858A or MAX5856A PLL enabled;
JU1, JU10, and JU11 installed;
JU4 not installed
CLKD mode
MAX5858 or MAX5858A, or MAX5856A PLL
disabled; JU1, JU10, and JU11 not installed;
JU4 installed
Table 9. Input Clock Selection
MAX5856A
PIN NAME
DA7/PD
DA6/
DACEN
DA5/
F2EN
DA4/
F1EN
DA3/G3
DA2/G2
DA1/G1
DA0/G0
SHORT
TO
DGND
SHORT
TO
DGND
MAX5858A
EV KIT
J1-41
J1-39
J1-37
J1-35
J1-33
J1-31
J1-29
J1-27
J1-25
J1-23
Table 7. MAX5856A Data Bits DB7 Through DB0 on the MAX5858A EV Kit
MAX5856A
PIN NAME
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SHORT
TO
DGND
SHORT
TO
DGND
CW
MAX5858A
EV KIT
J1-21
J1-19
J1-17
J1-15
J1-13
J1-11
J1-9
J1-7
J1-5
J1-3
J1-1
SHUNT
POSITION
PLLEN PIN
PLL CLOCK
MULTIPLIER
Not installed
Installed
Connected to PVDD with R29
Connected to PGND
Enabled
Disabled
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