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參數(shù)資料
| 型號(hào)： | MAX5878EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 250MSPS 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 14ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 331mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 250M |
MAX5878
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________
9
Pin Description
PIN
NAME
FUNCTION
1
B4N
Complementary Data Bit 4
2
B3P
Data Bit 3
3
B3N
Complementary Data Bit 3
4
B2P
Data Bit 2
5
B2N
Complementary Data Bit 2
6
B1P
Data Bit 1
7
B1N
Complementary Data Bit 1
8
B0P
Data Bit 0 (LSB)
9
B0N
Complementary Data Bit 0 (LSB)
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GND
Ground
11
DVDD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F
capacitor to GND.
14, 21, 22, 31,
32
AVDD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1F capacitor to GND.
16
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1F
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
17
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2k
resistor between FSADJ and DACREF. See Table 1.
18
DACREF
Current-Set Resistor Return Path. Internally connected to GND. Do not use as an external
ground connection.
19, 34
AVDD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1F capacitor to GND.
24
OUTQN
Complementary Q-DAC Output. Negative terminal for current output.
25
OUTQP
Q-DAC Output. Positive terminal for current output.
28
OUTIN
Complementary I-DAC Output. Negative terminal for current output.
29
OUTIP
I-DAC Output. Positive terminal for current output.
35
AVCLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1F
capacitor to GND.
37
CLKN
Complementary Converter Clock Input. Negative input terminal for differential converter clock.
Internally biased to AVCLK / 2.
38
CLKP
Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to
AVCLK / 2.
39
TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format.
TORB has an internal pulldown resistor.
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