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參數(shù)資料
| 型號： | MAX5874EGK+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT DUAL 200MSPS 68-QFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 設置時間： | 14ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 68-QFN 裸露焊盤（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 200M |
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________
15
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified. For a
DAC, the deviations are measured at every individual
step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actu-
al step height and the ideal value of 1 LSB. A DNL error
specification of less than 1 LSB guarantees a monoton-
ic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Dynamic Performance Parameter Definitions
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog output (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum can
be derived from the DAC’s resolution (N bits):
SNR = 6.02 x N + 1.76
However, noise sources such as thermal noise, reference
noise, clock jitter, etc., affect the ideal reading; therefore,
SNR is computed by taking the ratio of the RMS signal to
the RMS noise, which includes all spectral components
minus the fundamental, the first four harmonics, and the
DC offset.
Noise Spectral Density
The DAC output noise floor is the sum of the quantiza-
tion noise and the output amplifier noise (thermal and
shot noise). Noise spectral density is the noise power in
1Hz bandwidth, specified in dBFS/Hz.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal components) to the RMS value
of their next-largest distortion component. SFDR is usual-
ly measured in dBc and with respect to the carrier fre-
quency amplitude or in dBFS with respect to the DAC’s
full-scale range. Depending on its test condition, SFDR is
observed within a predefined window or to Nyquist.
Two-Tone Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in dBc (or dBFS)
of the worst 3rd-order (or higher) IMD product(s) to either
output tone.
Adjacent Channel Leakage Power Ratio (ACLR)
Commonly used in combination with wideband code-
division multiple-access (W-CDMA), ACLR reflects the
leakage power ratio in dB between the measured
power within a channel relative to its adjacent channel.
ACLR provides a quantifiable method of determining
out-of-band spectral energy and its influence on an
adjacent channel when a bandwidth-limited RF signal
passes through a nonlinear device.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the converter’s specified accuracy.
Glitch Impulse
A glitch is generated when a DAC switches between two
codes. The largest glitch is usually generated around the
midscale transition, when the input pattern transitions from
011...111 to 100...000. The glitch impulse is found by inte-
grating the voltage of the glitch at the midscale transition
over time. The glitch impulse is usually specified in pVs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5874EVKIT | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Evaluation Kit for the MAX5873 MAX5874 MAX5875 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5875EGK | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| MAX5875EGK+D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit 2Ch 200Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5875EGK+TD | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 16-Bit 2Ch 200Msps DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| MAX5875EGK-D | 功能描述:數(shù)模轉(zhuǎn)換器- DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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